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Commit Graph

119321 Commits

Author SHA1 Message Date
JF Bastien
a3917826ee WebAssembly: add basic int/fp instruction codegen.
Summary: This patch has the most basic instruction codegen for 32 and 64 bit int/fp.

Reviewers: sunfish

Subscribers: llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11193

llvm-svn: 242201
2015-07-14 21:13:29 +00:00
Krzysztof Parzyszek
298d193f94 Fix NDEBUG build warning
llvm-svn: 242200
2015-07-14 21:03:24 +00:00
Tim Northover
e8970888a4 GVN: tolerate an instruction being replaced without existing in the leaderboard
Sometimes an incidentally created instruction can duplicate a Value used
elsewhere. It then often doesn't end up in the leader table. If it's later
removed, we attempt to remove it from the leader table and segfault.

Instead we should just ignore the removal request, which won't cause any
problems. The reverse situation, where the original instruction is replaced by
the new one (which you might think could leave the leader table empty) cannot
occur, because the incidental instruction will never be found in the first
place.

llvm-svn: 242199
2015-07-14 21:03:18 +00:00
Hans Wennborg
04dec99648 test-release.sh: Remove the InstallDir parameter from configure_llvmCore
After r242187, it's never set.

llvm-svn: 242194
2015-07-14 20:15:15 +00:00
Krzysztof Parzyszek
c75f57b597 Fix Windows build: replace __func__ with LLVM_FUNCTION_NAME
llvm-svn: 242192
2015-07-14 20:11:28 +00:00
Bruno Cardoso Lopes
e7925ee6f8 [MMX] Use the appropriate instructions for GR64 <-> VR64 copies.
MOVSDto64rr and MOV64toSDrr are defined to convert between FR64 (%xmm)
<-> GR64 registers, not VR64 (%mm) <-> GR64. This is wrong.

I found this by inspection and could not find a suitable testcase for it
since (1) we don't handle MMX bitcasts in Peephole optimizer as to
generate COPYs that (2) could be expanded back to the appropriate x86
instruction in ExpandPostRA.

Switch to use the appropriate instructions: MMX_MOVD64from64rr and
MMX_MOVD64to64rr here.

llvm-svn: 242191
2015-07-14 20:09:34 +00:00
Hal Finkel
7783df1bb4 [PowerPC] Fix the PPCInstrInfo::getInstrLatency implementation
PowerPC uses itineraries to describe processor pipelines (and dispatch-group
restrictions for P7/P8 cores). Unfortunately, the target-independent
implementation of TII.getInstrLatency calls ItinData->getStageLatency, and that
looks for the largest cycle count in the pipeline for any given instruction.
This, however, yields the wrong answer for the PPC itineraries, because we
don't encode the full pipeline. Because the functional units are fully
pipelined, we only model the initial stages (there are no relevant hazards in
the later stages to model), and so the technique employed by getStageLatency
does not really work. Instead, we should take the maximum output operand
latency, and that's what PPCInstrInfo::getInstrLatency now does.

This caused some test-case churn, including two unfortunate side effects.
First, the new arrangement of copies we get from function parameters now
sometimes blocks VSX FMA mutation (a FIXME has been added to the code and the
test cases), and we have one significant test-suite regression:

SingleSource/Benchmarks/BenchmarkGame/spectral-norm
	56.4185% +/- 18.9398%

In this benchmark we have a loop with a vectorized FP divide, and it with the
new scheduling both divides end up in the same dispatch group (which in this
case seems to cause a problem, although why is not exactly clear). The grouping
structure is hard to predict from the bottom of the loop, and there may not be
much we can do to fix this.

Very few other test-suite performance effects were really significant, but
almost all weakly favor this change. However, in light of the issues
highlighted above, I've left the old behavior available via a
command-line flag.

llvm-svn: 242188
2015-07-14 20:02:02 +00:00
Dan Liew
340a06db42 Fix several issues with the test-release.sh script
* Use the default install prefix (/usr/local) and use DESTDIR instead to
  set a temporary install location for tarballing. This is the correct
  way to package binary releases (otherwise the temporary install path
  ends up in files in the binary release).
* Remove ``-disable-clang`` option. It did not work correctly
  (tarballing assumed phase 3 was run) and when doing a release
  we should always be doing a three-phased build and test.

Note: Technically we should only be using DESTDIR for the third phase
and use --prefix for the first and second phase because we run the built
clang from phase 1 and 2 (and in general an application's behaviour
may depend on the install prefix). However in the case of clang it
seems to not care what the install prefix was so to simplify the script
we use DESTDIR for all three stages.

llvm-svn: 242187
2015-07-14 19:46:19 +00:00
Krzysztof Parzyszek
8d49f92601 [Hexagon] Generate instructions for operations on predicate registers
Convert logical operations on general-purpose registers to the correspon-
ding operations on predicate registers.

llvm-svn: 242186
2015-07-14 19:30:21 +00:00
Keno Fischer
400c1358d0 [CodeGen] Force emission of personality directive if explicitly specified
Summary:
Before this change, personality directives were not emitted
if there was no invoke left in the function (of course until
recently this also meant that we couldn't know what
the personality actually was). This patch forces personality directives
to still be emitted, unless it is known to be a noop in the absence of
invokes, or the user explicitly specified `nounwind` (and not
`uwtable`) on the function.

Reviewers: majnemer, rnk

Subscribers: rnk, llvm-commits

Differential Revision: http://reviews.llvm.org/D10884

llvm-svn: 242185
2015-07-14 19:22:51 +00:00
Richard Smith
36bdc10e75 Add support for on-disk hash table lookup with a known hash, for situations where the same key will be looked up in multiple tables.
llvm-svn: 242179
2015-07-14 18:40:59 +00:00
Yaron Keren
3a9f7c2dd9 Teach config.guess that MSYS exists.
We might not want to upgrade config.guess to the current
version due to the license change from GPL2 to GPL3.

llvm-svn: 242178
2015-07-14 18:33:55 +00:00
Matt Arsenault
efaaa8cb7c AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)
This can be done only with moves which theoretically
will optimize better later.

Although this transform increases the instruction count,
it should be code size / cycle count neutral in the worst
VALU case. It also seems to slightly improve a couple
of testcases due to other DAG combines this exposes.

This is probably slightly worse for the SALU case, so
it might be better to handle this during moveToVALU,
although then you lose some simplifications like
the load width reducing in the simple testcase.

llvm-svn: 242177
2015-07-14 18:20:33 +00:00
Matt Arsenault
988dd980cf AMDGPU/SI: Fix read2 merging into a super register.
If the read2 produced was supposed to be writing into a
super register, it would use the wrong subregister indices.
Fix this by inserting copies, so we only ever write to a vreg_64.
Run the register coalescer again to clean this up, although this
isn't ideal and often does result in an extra move.

Also remove the assert that offset1 > offset0.

There isn't a real reason to not allow this other than a minor
convenience in the compiler, and it doesn't seem worth the effort
of avoiding it.

llvm-svn: 242174
2015-07-14 17:57:36 +00:00
Matthias Braun
004fe44fe3 MachineRegisterInfo: Remove UsedPhysReg infrastructure
We have a detailed def/use lists for every physical register in
MachineRegisterInfo anyway, so there is little use in maintaining an
additional bitset of which ones are used.

Removing it frees us from extra book keeping. This simplifies
VirtRegMap.

Differential Revision: http://reviews.llvm.org/D10911

llvm-svn: 242173
2015-07-14 17:52:07 +00:00
David Blaikie
8b683dda3c Avoid MSVC-incompatible use of init list.
llvm-svn: 242170
2015-07-14 17:40:53 +00:00
Matthias Braun
e903448f74 RAGreedy: Keep track of allocated PhysRegs internally
Do not use MachineRegisterInfo::setPhysRegUsed()/isPhysRegUsed()
anymore. This bitset changes function-global state and is set by the
VirtRegRewriter anyway.
Simply use a bitvector private to RAGreedy.

Differential Revision: http://reviews.llvm.org/D10910

llvm-svn: 242169
2015-07-14 17:38:17 +00:00
Nemanja Ivanovic
a397908a1f Add missing builtins to the PPC back end for ABI compliance (vol. 4)
This patch corresponds to review:
http://reviews.llvm.org/D11183

Back end portion of the fourth round of additions to altivec.h.

llvm-svn: 242167
2015-07-14 17:25:20 +00:00
Tim Northover
b5aedb0d34 ARM: add at least one real test for r242123.
The ones committed were orthogonal to the change and would have passed before
that revision. What it *did* do was prevent an assertion failure when
generating object files.

llvm-svn: 242166
2015-07-14 17:23:55 +00:00
Matthias Braun
14b971e075 PrologEpilogInserter: Rewrite API to determine callee save regsiters.
This changes TargetFrameLowering::processFunctionBeforeCalleeSavedScan():

- Rename the function to determineCalleeSaves()
- Pass a bitset of callee saved registers by reference, thus avoiding
  the function-global PhysRegUsed bitset in MachineRegisterInfo.
- Without PhysRegUsed the implementation is fine tuned to not save
  physcial registers which are only read but never modified.

Related to rdar://21539507

Differential Revision: http://reviews.llvm.org/D10909

llvm-svn: 242165
2015-07-14 17:17:13 +00:00
Tim Northover
9509e14e0a AArch64: add rev64 alias for 64-bit rev instruction.
It could be useful to assembly programmers and makes the permitted variants a
little more uniform.

llvm-svn: 242164
2015-07-14 17:07:29 +00:00
Krzysztof Parzyszek
38a34d7651 [Hexagon] Generate "extract" instructions more aggressively
Generate extract instructions (via intrinsics) before the DAG combiner
folds shifts into unrecognizable forms.

llvm-svn: 242163
2015-07-14 17:07:24 +00:00
Rafael Espindola
1893c5e76b llvm-ar: Don't try to extract from thin archives.
This matches the gnu ar behavior.

llvm-svn: 242162
2015-07-14 16:55:13 +00:00
Hans Wennborg
9a2398fd87 ARMAsmParser: Take MCInst param by const-ref
(Broken out from http://reviews.llvm.org/D11167)

llvm-svn: 242160
2015-07-14 16:39:01 +00:00
David Blaikie
860ce3d2ca Add default value for Args parameter of IRBuilder::CreateCall
Convenient for calls to zero-argument functions.

Patch by servuswiegehtz at yahoo.de

llvm-svn: 242159
2015-07-14 16:38:30 +00:00
Rafael Espindola
1724f6ab47 Sleep for 2.1 seconds to see if that makes the test stable on windows.
Might fix pr24106.

llvm-svn: 242158
2015-07-14 16:34:23 +00:00
Hans Wennborg
9a64836fb3 Allocate the IntervalMap in ELF.h on the heap to work around MSVC alignment bug (PR24113)
llvm-svn: 242157
2015-07-14 16:27:16 +00:00
Rafael Espindola
e5753ae917 llvm-ar: print an error when the requested member is not found.
llvm-svn: 242156
2015-07-14 16:02:40 +00:00
Rafael Espindola
98eeaa500c Use a range loop. NFC.
llvm-svn: 242153
2015-07-14 15:22:42 +00:00
JF Bastien
0e7c6963b3 Revert "Fix llvm-config to emit the linker flag for the combined shared object built by autoconfig/make instead of the individual components."
This reverts commit 01446706b4c0a86bb64768f307079cab5c514aa3.

Causes breakage, seems to be related to 'svn' in the file's name:

  CC=gcc CXX=g++ \
  ../llvm/configure \
    --prefix=/usr \
    --sysconfdir=/etc \
    --enable-shared \
    --enable-libffi \
    --enable-targets=all \
    --disable-assertions \
    --with-python=/usr/bin/python2 \
    --enable-optimized

  make REQUIRES_RTTI=1 ENABLE_PIC=1

results:
llvm[2]: Linking Release unit test Support (without symbols)
llvm[2]: ======= Finished Linking Release Unit test Support (without symbols)
make[3]: Entering directory '/build/llvm-svn/src/build/bindings/ocaml/llvm'
make[3]: *** No rule to make target '/build/llvm-
svn/src/build/Release/lib/ocaml/libLLVM-3.7.0svn.so', needed by 'build-
deplibs'.  Stop.
make[3]: *** Waiting for unfinished jobs....
llvm[3]: Compiling llvm_ocaml.c for Release build
make[3]: Leaving directory '/build/llvm-svn/src/build/bindings/ocaml/llvm'
/build/llvm-svn/src/llvm/Makefile.rules:880: recipe for target 'all' failed
/build/llvm-svn/src/llvm/Makefile.rules:965: recipe for target 'all' failed

Differential Revision: http://reviews.llvm.org/D10716

llvm-svn: 242152
2015-07-14 15:10:34 +00:00
Rafael Espindola
926701ff8f Rename a test. NFC.
llvm-svn: 242151
2015-07-14 15:06:18 +00:00
Alexandros Lamprineas
ab09d355ed Caused regressions: compile Release+Asserts failed on clang-native-arm-cortex-a9
Revert "-Added API for retrieving the default FPU of a CPU from TargetParser."

This reverts commit 01199ab0c6ff2d5c4f6b2c05a95ec011e41c4669.

llvm-svn: 242147
2015-07-14 14:34:06 +00:00
Tom Stellard
a3220fa789 AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11061

llvm-svn: 242146
2015-07-14 14:15:03 +00:00
Aaron Ballman
4fd74dc826 Silencing two MSVC warnings; 'argument' : truncation from 'unsigned int' to 'int16_t' and truncation of constant value. NFC intended.
llvm-svn: 242145
2015-07-14 14:14:00 +00:00
Alexandros Lamprineas
50607c3d92 -Added API for retrieving the default FPU of a CPU from TargetParser.
-Implemented as a table lookup.

Change-Id: Ibf7217f6bd2769e9c06835a5aede3d072dee6757
Phabricator: http://reviews.llvm.org/D11100
llvm-svn: 242141
2015-07-14 13:20:48 +00:00
Daniel Sanders
1c28346cdb [mips] Fix li/la differences between IAS and GAS.
Summary:
- Signed 16-bit should have priority over unsigned.
- For la, unsigned 16-bit must use ori+addu rather than directly use ori.
- Correct tests on 32-bit immediates with 64-bit predicates by
  sign-extending the immediate beforehand. For example, isInt<16>(0xffff8000)
  should be true and use addiu.

Also split li/la testing into separate files due to their size.

Reviewers: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10967

llvm-svn: 242139
2015-07-14 12:24:22 +00:00
Chandler Carruth
7be73698e4 [PM/AA] Reformat GlobalsModRef so that subsequent patches I make here
don't continually introduce formatting deltas. NFC

llvm-svn: 242129
2015-07-14 08:42:39 +00:00
Petr Pavlu
a6f53f4b75 Fix comment typo
Test commit access.

llvm-svn: 242128
2015-07-14 08:00:34 +00:00
David Majnemer
52d04298e1 [SROA] Don't de-atomic volatile loads and stores
Volatile loads and stores are made visible in global state regardless of
what memory is involved.  It is not correct to disregard the ordering
and synchronization scope because it is possible to synchronize with
memory operations performed by hardware.

This partially addresses PR23737.

llvm-svn: 242126
2015-07-14 06:19:58 +00:00
Yaron Keren
a300c4d7e5 Generate correct asm info for mingw and cygwin ARM targets.
http://reviews.llvm.org/D11075

Patch by Martell Malone
Reviewed by Reid Kleckner

llvm-svn: 242123
2015-07-14 05:51:05 +00:00
NAKAMURA Takumi
07289582f7 [CMake] Unbreak add_llvm_external_project when external projects are specified.
LLVM_EXTERNAL_*_SOURCE_DIR is reset as PATH with set(CACHE PATH).
Then the CACHE PATH variable, LLVM_EXTERNAL_*_SOURCE_DIR, is normalized as
${CMAKE_SOURCE_DIR}/${path_var} if ${path_var} is relative.

llvm-svn: 242120
2015-07-14 05:12:53 +00:00
NAKAMURA Takumi
6033cde4ab Prune trailing whitespaces and CRs.
llvm-svn: 242117
2015-07-14 04:03:49 +00:00
NAKAMURA Takumi
aa66e39b4d Give an explicit triple to llvm/test/CodeGen/X86/pr13577.ll.
llvm-svn: 242111
2015-07-14 03:07:06 +00:00
Matthias Braun
e1bcc14506 Revert "LegalizeDAG: Fix and improve FCOPYSIGN/FABS legalization"
Accidental commit, needs review first.

This reverts commit r242107.

llvm-svn: 242108
2015-07-14 02:09:57 +00:00
Matthias Braun
e8ffab6ec5 LegalizeDAG: Fix and improve FCOPYSIGN/FABS legalization
- Factor out code to query and modify the sign bit of a floatingpoint
  value as an integer. This also works if none of the targets integer
  types is big enough to hold all bits of the floatingpoint value.

- Legalize FABS(x) as FCOPYSIGN(x, 0.0) if FCOPYSIGN is available,
  otherwise perform bit manipulation on the sign bit. The previous code
  used "x >u 0 ? x : -x" which is incorrect for x being -0.0! It also
  takes 34 instructions on ARM Cortex-M4. With this patch we only
  require 5:
    vldr d0, LCPI0_0
    vmov r2, r3, d0
    lsrs r2, r3, #31
    bfi r1, r2, #31, #1
    bx lr
  (This could be further improved if the compiler would recognize that
   r2, r3 is zero).

- Only lower FCOPYSIGN(x, y) = sign(x) ? -FABS(x) : FABS(x) if FABS is
  available otherwise perform bit manipulation on the sign bit.

- Perform the sign(x) test by masking out the sign bit and comparing
  with 0 rather than shifting the sign bit to the highest position and
  testing for "<s 0". For x86 copysignl (on 80bit values) this gets us:
    testl $32768, %eax
  rather than:
    shlq $48, %rax
    sets %al
    testb %al, %al

llvm-svn: 242107
2015-07-14 02:08:26 +00:00
Matthias Braun
cc6f791568 X86: Check output of x86 copysignl testcase.
This makes the changes in an upcoming patch visible.

llvm-svn: 242106
2015-07-14 02:08:23 +00:00
Andrew Wilkins
4d5120d513 Add capability to get and set the personalitty function from the C API
Summary:
The capability was lost with D10429 where the personality function was set at function level rather than landing pad level. Now there is no way to get/set the personality function from the C API. That is a problem.

Note that the whole thing could be avoided by improving the C API testing, as started by D10725

Reviewers: chandlerc, bogner, majnemer, andrew.w.kaylor, rafael, rnk, axw

Subscribers: rafael, llvm-commits

Differential Revision: http://reviews.llvm.org/D10946

llvm-svn: 242104
2015-07-14 01:23:06 +00:00
Chris Bieneman
e9b932f094 [CMake] Forgot to quote the first part of STREQUAL.
llvm-svn: 242103
2015-07-14 01:19:07 +00:00
Chris Bieneman
efe18d13a6 [CMake] We shouldn't be storing values in the cache unless they actually need CMake cache behavior.
add_llvm_external_project puts LLVM_EXTERNAL_${nameUPPER}_SOURCE_DIR into the cache even if it is just the in-tree default path. This causes all sorts of oddness, and makes it so that I can't change the behavior of this variable.

This patch never puts LLVM_EXTERNAL_${nameUPPER}_SOURCE_DIR into the cache. It will only end up in the cache if it is specified on the command line, which is the correct behavior.

There is also a temporary change to remove non-default values from the cache if they are already present. This should have the impact of cleaning out unncecissary values from the caches on the buildbots and people's local build directories. This part of the change is marked with a TODO and can be removed in a few days.

llvm-svn: 242102
2015-07-14 01:17:43 +00:00
Rafael Espindola
dc111c1ec7 Add a herper function. NFC.
llvm-svn: 242100
2015-07-14 01:06:16 +00:00