Vladimir Medic
841be82cec
This patch fixes a bug in floating point operands parsing, when instruction alias uses default register operand.
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llvm-svn: 194562
2013-11-13 09:48:53 +00:00
Vladimir Medic
c143ef4d9e
This patch implements Mips load/store instructions from/to coprocessor 2. Test cases are added.
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llvm-svn: 190780
2013-09-16 10:29:42 +00:00
Vladimir Medic
5010b6deef
Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of register when PFU is 32 bit.
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llvm-svn: 190397
2013-09-10 09:50:01 +00:00
Akira Hatanaka
2236f78fa4
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.
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Also, fix predicates.
llvm-svn: 189432
2013-08-28 00:55:15 +00:00
Akira Hatanaka
5d76bb1499
[mips] Fix instruction definitions that were incorrectly marked as code-gen-only.
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llvm-svn: 188690
2013-08-19 19:08:03 +00:00
Vladimir Medic
aafcb477fd
This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.
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llvm-svn: 187410
2013-07-30 10:12:14 +00:00
Akira Hatanaka
39a746e93f
[mips] Fix MipsAsmParser::parseCCRRegs.
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Enable parsing all 32 floating point control registers $0-31 and stop trying to
parse floating point condition code register $fcc0. Also, return ParseFail if
the operand being parsed is not in the expected format.
llvm-svn: 186861
2013-07-22 19:30:38 +00:00
Vladimir Medic
0a645b02e5
This patch extends mips register parsing methods to allow indexed register parsing. The corresponding test cases are added to the patch.
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llvm-svn: 186567
2013-07-18 09:28:35 +00:00
Jack Carter
6a3d1c59be
Mips assembler: Explicit floating point condition register recognition.
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This patch allows the assembler to recognize $fcc0
as a valid register for conditional move instructions.
Corresponding test cases have been added.
Contributer: Vladimir Medic
llvm-svn: 179567
2013-04-15 22:21:55 +00:00
Nico Rieck
3863b37eaf
Use object file specific section type for initial text section
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llvm-svn: 179494
2013-04-14 21:18:36 +00:00
Jack Carter
c5f946b170
Adding support for instructions mfc0, mfc2, mtc0, mtc2
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move from and to coprocessors 0 and 2.
Contributer: Vladimir Medic
llvm-svn: 165351
2012-10-06 01:17:37 +00:00
Jack Carter
0a824e63ab
The Mips standalone assembler fpu instruction support.
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Test cases included
Contributer: Vladimir Medic
llvm-svn: 163363
2012-09-07 00:23:42 +00:00
