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8 Commits

Author SHA1 Message Date
Andrew Trick
d09b64fc25 Instruction scheduling itinerary for Intel Atom. 
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.

Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.

Adds a test to verify that the scheduler is working.

Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.

Patch by Preston Gurd!

llvm-svn: 149558
 2012-02-01 23:20:51 +00:00
NAKAMURA Takumi
00228d0c2c Triple::MinGW64 is deprecated and removed. We can use Triple::MinGW32 generally. 
No one uses *-mingw64. mingw-w64 is represented as {i686|x86_64}-w64-mingw32. In llvm side, i686 and x64 can be treated as similar way.

llvm-svn: 125747
 2011-02-17 12:24:17 +00:00
NAKAMURA Takumi
07a84f5950 Target/X86: Tweak allocating shadow area (aka home) on Win64. It must be enough for caller to allocate one. 
llvm-svn: 124949
 2011-02-05 15:11:32 +00:00
Duncan Sands
ed2ef5a987 Correct some bogus target triples. 
llvm-svn: 103265
 2010-05-07 17:03:48 +00:00
Dan Gohman
df2896d609 Eliminate more uses of llvm-as and llvm-dis. 
llvm-svn: 81290
 2009-09-08 23:54:48 +00:00
Dan Gohman
bf08e82d8e Remove obsolete -f flags. 
llvm-svn: 79992
 2009-08-25 15:38:29 +00:00
Anton Korobeynikov
0bac80c138 Unbreak Win64 CC. Step one: honour register save area, fix some alignment and provide a different set of call-clobberred registers. 
llvm-svn: 77962
 2009-08-03 08:12:53 +00:00
Eli Friedman
11070e275f PR3739, part 2: Use an explicit store to spill XMM registers. (Previously, 
the code tried to use "push", which doesn't exist for XMM registers.)

llvm-svn: 72836
 2009-06-04 02:32:04 +00:00