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Commit Graph

7649 Commits

Author SHA1 Message Date
Anton Korobeynikov
a6a4ed92ee Really fix the test. Sorry for the breakage...
llvm-svn: 185369
2013-07-01 19:51:36 +00:00
Anton Korobeynikov
8e5dfb5ca4 Fix the test which relies on uncommitted change
llvm-svn: 185368
2013-07-01 19:50:31 +00:00
Anton Korobeynikov
f6e50fd093 Add jump tables handling for MSP430.
Patch by Job Noorman!

llvm-svn: 185364
2013-07-01 19:44:44 +00:00
Cameron Zwarich
7af5158621 Fix PR16508.
When phis get lowered, destination copies are inserted using an iterator that is
determined once for all phis in the block, which BuildMI interprets as a request
to insert an instruction directly before the iterator. In the case of a cyclic
phi, source copies may also be inserted directly before this iterator, which can
cause source copies to be inserted before destination copies. The fix is to keep
an iterator to the last phi and then advance it while lowering each phi in order
to insert destination copies directly after the phis.

llvm-svn: 185363
2013-07-01 19:42:46 +00:00
Hal Finkel
0b854b8c04 Don't form PPC CTR loops for over-sized exit counts
Although you can't generate this from C on PPC64, if you have a loop using a
64-bit counter on PPC32 then you can't form a CTR-based loop for it. This had
been cauing the PPCCTRLoops pass to assert.

Thanks to Joerg Sonnenberger for providing a test case!

llvm-svn: 185361
2013-07-01 19:34:59 +00:00
Tim Northover
c1348880dc AArch64: correct CodeGen of MOVZ/MOVK combinations.
According to the AArch64 ELF specification (4.6.8), it's the
assembler's responsibility to make sure the shift amount is correct in
relocated MOVZ/MOVK instructions.

This wasn't being obeyed by either the MCJIT CodeGen or RuntimeDyldELF
(which happened to work out well for JIT tests). This commit should
make us compliant in this area.

llvm-svn: 185360
2013-07-01 19:23:10 +00:00
Tim Northover
51fd747de9 Revert r185339 (ARM: relax the atomic release barrier to "dmb ishst")
Turns out I'd misread the architecture reference manual and thought
that was a load/store-store barrier, when it's not.

Thanks for pointing it out Eli!

llvm-svn: 185356
2013-07-01 18:37:33 +00:00
Tim Northover
25286e5b71 ARM: relax the atomic release barrier to "dmb ishst"
I believe the full "dmb ish" barrier is not required to guarantee release
semantics for atomic operations. The weaker "dmb ishst" prevents previous
operations being reordered with a store executed afterwards, which is enough.

A key point to note (fortunately already correct) is that this barrier alone is
*insufficient* for sequential consistency, no matter how liberally placed.

llvm-svn: 185339
2013-07-01 14:48:48 +00:00
Justin Holewinski
d88c5d6e19 [NVPTX] Add support for module-scope inline asm
Since we were explicitly not calling AsmPrinter::doInitialization,
any module-scope inline asm was not being printed.

llvm-svn: 185336
2013-07-01 13:00:14 +00:00
Justin Holewinski
89a1f98197 [NVPTX] 64-bit ADDC/ADDE are not legal
llvm-svn: 185333
2013-07-01 12:59:04 +00:00
Justin Holewinski
6284a5cea6 [NVPTX] Fix vector loads from parameters that span multiple loads, and fix some typos
llvm-svn: 185332
2013-07-01 12:59:01 +00:00
Justin Holewinski
77ba2f5ed9 [NVPTX] Handle signext/zeroext attributes properly
Fix a case where we were incorrectly sign-extending a value when we should have been zero-extending the value.

Also change some SIGN_EXTEND to ANY_EXTEND because we really dont care and may have more opportunity to fold subexpressions

llvm-svn: 185331
2013-07-01 12:58:58 +00:00
Justin Holewinski
46fe052e1f [NVPTX] Add support for native SIGN_EXTEND_INREG where available
llvm-svn: 185330
2013-07-01 12:58:56 +00:00
Justin Holewinski
46d3cad4d8 [NVPTX] Add isel patterns for [reg+offset] form of ldg/ldu.
llvm-svn: 185329
2013-07-01 12:58:52 +00:00
Justin Holewinski
c254f0f839 [NVPTX] Make sure we zero out high-order 24 bits for 8-bit load into 32-bit value
llvm-svn: 185328
2013-07-01 12:58:48 +00:00
Vincent Lejeune
4cef82fa31 R600: Support schedule and packetization of trans-only inst
llvm-svn: 185268
2013-06-29 19:32:43 +00:00
Hal Finkel
055ca2ecc9 PPC: Ignore spill/restore requests for VRSAVE (except on Darwin)
This fixes PR16418, which reports that a function calling
__builtin_unwind_init() asserts. The cause is that this generates a
spill/restore for VRSAVE, and we support that only on Darwin (because VRSAVE is
only really used on Darwin).

The test case checks only that we don't crash. We can add correctness checks
once someone verifies what behavior the function is supposed to have.

llvm-svn: 185235
2013-06-28 22:29:56 +00:00
Hal Finkel
49c072c532 Fix CodeGen/PowerPC/stack-protector.ll on OpenBSD
On OpenBSD, the stack-smash protection transform uses "__guard_local"
and "__stack_smash_handler" instead of "__stack_chk_guard" and
"__stack_chk_fail".  However, CodeGen/PowerPC/stack-protector.ll
doesn't specify a target OS, so on OpenBSD it fails.

Add -mtriple=ppc32-unknown-linux to make the test host-OS agnostic. While
there, convert to FileCheck.

Patch by Matthew Dempsky.

llvm-svn: 185206
2013-06-28 20:18:14 +00:00
Hal Finkel
7f9144ae20 Fix a PPC rlwimi instruction-selection bug
Under certain (evidently rare) circumstances, this code used to convert OR(a,
AND(x, y)) into OR(a, x). This was incorrect.

While there, I've added a comment to the code immediately above.

llvm-svn: 185201
2013-06-28 20:00:07 +00:00
Lang Hames
e8b20c4f7b Add missing case to switch statement - DAGTypeLegalizer::ExpandIntegerResult
should expand ATOMIC_CMP_SWAP nodes the same way that it does for ATOMIC_SWAP.

Since ATOMIC_LOADs on some targets (e.g. older ARM variants) get legalized to
ATOMIC_CMP_SWAPs, the missing case had been causing i64 atomic loads to crash
during isel.

<rdar://problem/14074644>

llvm-svn: 185186
2013-06-28 18:36:42 +00:00
Justin Holewinski
434a514175 [NVPTX] Add (1.0 / sqrt(x)) => rsqrt(x) generation when allowable by FP flags
llvm-svn: 185178
2013-06-28 17:58:13 +00:00
Justin Holewinski
f17855a9dc [NVPTX] Calling conventions fix
Fix ABI handling for function
returning bool -- use st.param.b32 to return the value
and use ld.param.b32 in caller to load the return value.

llvm-svn: 185177
2013-06-28 17:58:10 +00:00
Justin Holewinski
6feb5e8392 [NVPTX] Add support for cttz/ctlz/ctpop
llvm-svn: 185176
2013-06-28 17:58:07 +00:00
Justin Holewinski
d365a376eb [NVPTX] Clean up comparison/select/convert patterns and factor out PTX instructions from their patterns
Test case is no breakage

llvm-svn: 185175
2013-06-28 17:58:04 +00:00
Justin Holewinski
0f70140107 [NVPTX] Remove i8 register class. PTX support for i8 (.b8, .u8, .s8) is rather poor and we're better off just ignoring it and letting LLVM expand all i8 ops out to i16.
llvm-svn: 185174
2013-06-28 17:57:59 +00:00
Justin Holewinski
9ae87e685a [NVPTX] Add support for vectorized function return values
llvm-svn: 185173
2013-06-28 17:57:55 +00:00
Justin Holewinski
7332dc0027 [NVPTX] Clean up handling of formal arguments and enable generation of vector parameter loads
llvm-svn: 185172
2013-06-28 17:57:53 +00:00
Weiming Zhao
b97c1a69a2 Bug 13662: Enable GPRPair for all i64 operands of inline asm on ARM
This patch assigns paired GPRs  for inline asm with
64-bit data on ARM. It's enabled for both ARM and Thumb to support modifiers
like %H, %Q, %R.

llvm-svn: 185169
2013-06-28 17:26:02 +00:00
Tom Stellard
99f122e9be R600: Add local memory support via LDS
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 185162
2013-06-28 15:47:08 +00:00
Tom Stellard
97e3c49801 R600: Add support for GROUP_BARRIER instruction
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 185161
2013-06-28 15:46:59 +00:00
Tim Northover
e13264c995 ARM: ensure fixed-point conversions have sane types
We were generating intrinsics for NEON fixed-point conversions that didn't
exist (e.g. float -> i16). There are two cases to consider:
  + iN is smaller than float. In this case we can do the conversion but need an
    extend or truncate as well.
  + iN is larger than float. In this case using the NEON conversion would be
    incorrect so we don't perform any combining.

llvm-svn: 185158
2013-06-28 15:29:25 +00:00
Manman Ren
5bedd08922 Debug Info: clean up usage of Verify.
No functionality change.
It should suffice to check the type of a debug info metadata, instead of
calling Verify. For cases where we know the type of a DI metadata, use
assert.

Also update testing cases to make them conform to the format of DI classes.

llvm-svn: 185135
2013-06-28 05:43:10 +00:00
Tom Stellard
e3160dde2c R600: Remove alu-split.ll test
The purpose of this test was to check boundary conditions for the size
of an ALU clause.  This test is very sensitive to changes to the
optimizer or scheduler, because it requires an exact number of ALU
instructions in order to remain valid.  It's not good to have a test
this sensitive, because it is confusing to developers who implement
optimizations and then 'break' the test.

I'm not sure if there is a good way to test these limits using lit, but
if I can come up with replacement test that isn't as sensitive I'll add
it back to the tree.

llvm-svn: 185084
2013-06-27 17:00:38 +00:00
Joey Gouly
42f1898415 Add a Subtarget feature 'v8fp' to the ARM backend.
llvm-svn: 185073
2013-06-27 11:49:26 +00:00
Richard Sandiford
56466fde7f [SystemZ] Fix some embarrassing test typos
llvm-svn: 185070
2013-06-27 09:49:34 +00:00
Richard Sandiford
609a7eb0a1 [SystemZ] Allow LA and LARL to be rematerialized
llvm-svn: 185069
2013-06-27 09:42:10 +00:00
Richard Sandiford
a2d164d53e [SystemZ] Allow immediate moves to be rematerialized
llvm-svn: 185068
2013-06-27 09:38:48 +00:00
Richard Sandiford
964ffa104f [SystemZ] Add conditional store patterns
Add pseudo conditional store instructions, so that we use:

    branch foo:
    store
foo:

instead of:

    load
    branch foo:
    move
foo:
    store

z196 has real 32-bit and 64-bit conditional stores, but we don't use
any z196 instructions yet.

llvm-svn: 185065
2013-06-27 09:27:40 +00:00
Akira Hatanaka
1f2c22ad07 [mips] Improve code generation for constant multiplication using shifts, adds and
subs.

llvm-svn: 185011
2013-06-26 18:48:17 +00:00
Joey Gouly
f4bea6681b Add a subtarget feature 'v8' to the ARM backend.
This allows for targeting the ARMv8 AArch32 variant.

llvm-svn: 184967
2013-06-26 16:58:26 +00:00
Tim Northover
817190b1e4 ARM: allow predicated barriers in Thumb mode
The barrier instructions are only "always-execute" in ARM mode, they can quite
happily sit inside an IT block in Thumb.

llvm-svn: 184964
2013-06-26 16:52:32 +00:00
Joey Gouly
a82562fd5b Remove the 'generic' CPU from the ARM eabi attributes printer.
Make v4 the default ARM architecture attribute, to match CodeGen.

llvm-svn: 184962
2013-06-26 16:39:06 +00:00
Elena Demikhovsky
ea4d3808e5 Optimized integer vector multiplication operation by replacing it with shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const operand is not a splat constant vector.
llvm-svn: 184931
2013-06-26 10:55:03 +00:00
Tom Stellard
3854f648a8 R600: Use new getNamedOperandIdx function generated by TableGen
llvm-svn: 184880
2013-06-25 21:22:18 +00:00
Aaron Watry
d619f91b82 R600: Add v2i32 test for vselect
Note: Only adding test for evergreen, not SI yet.

When I attempted to expand vselect for SI, I got the following:
llc: /home/awatry/src/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:522:
llvm::SDValue llvm::DAGTypeLegalizer::PromoteIntRes_SETCC(llvm::SDNode*):
Assertion `SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
"Vector compare must return a vector result!"' failed.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 184847
2013-06-25 13:55:54 +00:00
Aaron Watry
1ee98e598b R600/SI: Expand xor v2i32/v4i32
Add test cases for both vector sizes on SI and also add v2i32 test for EG.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 184846
2013-06-25 13:55:52 +00:00
Aaron Watry
c7ec57ba3c R600: Add v2i32 test for setcc on evergreen
No test/expansion for SI has been added yet. Attempts to expand this
operation for SI resulted in a stacktrace in (IIRC) LegalizeIntegerTypes
which was complaining about vector comparisons being required to return
a vector type.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 184845
2013-06-25 13:55:49 +00:00
Aaron Watry
73046ba281 R600/SI: Expand urem of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.

Note: I followed the guidance of the v4i32 EG check... UREM produces really
complex code, so let's just check that the instruction was lowered
successfully.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 184844
2013-06-25 13:55:46 +00:00
Aaron Watry
c00dd00a32 R600/SI: Expand udiv v[24]i32 for SI and v2i32 for EG
Also add lit test for both cases on SI, and v2i32 for evergreen.

Note: I followed the guidance of the v4i32 EG check... UDIV produces really
complex code, so let's just check that the instruction was lowered
successfully.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 184843
2013-06-25 13:55:43 +00:00
Aaron Watry
0b4bbc3714 R600/SI: Expand ashr of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 184842
2013-06-25 13:55:40 +00:00