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Commit Graph

203806 Commits

Author SHA1 Message Date
Francesco Petrogalli
f1d24f0e57 [llvm][CodeGen] Do not scalarize llvm.masked.[gather|scatter] operating on scalable vectors.
This patch prevents the `llvm.masked.gather` and `llvm.masked.scatter` intrinsics to be scalarized when invoked on scalable vectors.

The change in `Function.cpp` is needed to prevent the warning that is raised when `getNumElements` is used in place of `getElementCount` on `VectorType` instances. The tests guards for regressions on this change.

The tests makes sure that calls to `llvm.masked.[gather|scatter]` are still scalarized when:

  # the intrinsics are operating on fixed size vectors, and
  # the compiler is not targeting fixed length SVE code generation.

Reviewed By: efriedma, sdesmalen

Differential Revision: https://reviews.llvm.org/D86249
2020-09-16 16:00:28 +00:00
Arthur Eubanks
825221f2e5 [NPM] Translate alias analysis into require<> as well
'require<globals-aa>' is needed to make globals-aa work in NPM, since
globals-aa is a module analysis but function passes cannot run module
analyses on demand.
So don't skip translating alias analyses to 'require<>'.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D87743
2020-09-16 08:54:09 -07:00
Dmitry Preobrazhensky
2ead9fa20c [AMDGPU] Corrected directive to use for ELF weak refs
WeakRefDirective should specify a directive to declare "a global as being a weak undefined symbol".
The directive used by AMDGPU was incorrect - ".weakref" was intended for other purposes.
The correct directive is ".weak" and it is already defined as default for ELF.
So the redefinition was removed.

Reviewers: arsenm, rampitec

Differential Revision: https://reviews.llvm.org/D87762
2020-09-16 18:51:26 +03:00
Simon Pilgrim
c2569d39e2 [X86] EmitInstrWithCustomInserter - remove redundant getDebugLoc() calls. NFCI.
Use the same DebugLoc that is called at the top of the method.

Fixes some Wshadow static analyzer warnings.
2020-09-16 16:29:56 +01:00
Mircea Trofin
2e97c41718 [NFC][Regalloc] accessors for 'reg' and 'weight'
Also renamed the fields to follow style guidelines.

Accessors help with readability - weight mutation, in particular,
is easier to follow this way.

Differential Revision: https://reviews.llvm.org/D87725
2020-09-16 08:28:57 -07:00
Matt Arsenault
f2aa3ef913 AMDGPU: Improve <2 x i24> arguments and return value handling
This was asserting for GlobalISel. For SelectionDAG, this was
passing this on the stack. Instead, scalarize this as if it were a
32-bit vector.
2020-09-16 11:21:56 -04:00
Sebastian Neubauer
6aba538d9d [AMDGPU] Add v3f16/v3i16 support to SDag
Fix lowering and instruction selection for v3x16 types
and enable InstCombine to emit them.

This patch only implements it for the selection dag.
GlobalISel tests in GlobalISel/llvm.amdgcn.image.load.1d.d16.ll and
GlobalISel/llvm.amdgcn.image.store.2d.d16.ll still don't work.

Differential Revision: https://reviews.llvm.org/D84420
2020-09-16 17:20:27 +02:00
Simon Pilgrim
eae470c498 [X86] Assert that we've found a terminator instruction. NFCI.
Fixes clang static analayzer null dereference warning.
2020-09-16 16:17:49 +01:00
Jay Foad
d11aa00c67 [AMDGPU] Enable scheduling around FP MODE-setting instructions
Pre-gfx10 all MODE-setting instructions were S_SETREG_B32 which is
marked as having unmodeled side effects, which makes the machine
scheduler treat it as a barrier. Now that we have proper implicit $mode
operands we can use a no-side-effects S_SETREG_B32_mode pseudo instead
for setregs that only touch the FP MODE bits, to give the scheduler more
freedom.

Differential Revision: https://reviews.llvm.org/D87446
2020-09-16 16:10:47 +01:00
Jay Foad
eea65ac487 [AMDGPU] Add -show-mc-encoding to setreg tests
This is a pre-commit for D87446 "[AMDGPU] Enable scheduling around FP MODE-setting instructions"
2020-09-16 16:09:47 +01:00
Simon Pilgrim
c3ae82fe83 [X86][SSE] Move VZEXT_MOVL(INSERT_SUBVECTOR(UNDEF,X,0)) handling into combineTargetShuffle.
Now that we're getting better at combining shuffles of different vector widths, this can now be performed as part of the standard target shuffle combines and isn't required for cleanup.

Exposed a minor issue in combineX86ShufflesRecursively where we failed to check if a shuffle's src ops were simple types.
2020-09-16 16:08:31 +01:00
Dangeti Tharun kumar
b31191fb60 [Partial Inliner] Compute intrinsic cost through TTI
https://bugs.llvm.org/show_bug.cgi?id=45932

assert(OutlinedFunctionCost >= Cloner.OutlinedRegionCost && "Outlined function cost should be no less than the outlined region") getting triggered in computeBBInlineCost.

Intrinsics like "assume" are considered regular function calls while computing costs.
This patch enables computeBBInlineCost to queries TTI for intrinsic call cost.

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D87132
2020-09-16 15:12:31 +01:00
Florian Hahn
bd672b8800 [DSE] Add another test cases with loop carried dependence. 2020-09-16 14:50:35 +01:00
Paul C. Anagnostopoulos
3fb53046bc Add section with details about DAGs. 2020-09-16 09:27:28 -04:00
Sanjay Patel
4abaadfc37 [SLP] fix formatting; NFC
Also move variable declarations closer to usage and add code comments.
2020-09-16 08:50:27 -04:00
Sam Parker
3322b6c5f2 [ARM] Reorder some logic
Re-order some checks in ValidateMVEInst.
2020-09-16 13:39:22 +01:00
Sanjay Patel
fe442597a7 [SLP] remove uses of 'auto' that obscure functionality; NFC 2020-09-16 08:26:21 -04:00
Sanjay Patel
838e7cb42b [SLP] remove redundant size check; NFC
We bail out on small array size anyway.
2020-09-16 08:11:19 -04:00
Sanjay Patel
2afe46fd57 [SLP] move loop index variable declaration to its use; NFC 2020-09-16 07:59:31 -04:00
Sanjay Patel
fec534536c [SLP] change poorly named variable; NFC
'V' shadows a function argument.
2020-09-16 07:59:31 -04:00
Sam Parker
f4c2727f1f [RDA] Fix getUniqueReachingDef for self loops
We've fixed the case where this could return an instruction after the
given instruction, but also means that we can falsely return a
'unique' def when they could be one coming from the backedge of a
loop.

Differential Revision: https://reviews.llvm.org/D87751
2020-09-16 12:44:23 +01:00
Sam Parker
51a8d5f1cd [ARM] Fix tail predication predicate tracking
Clear the CurrentPredicate when we find an instruction which would
completely overwrite the VPR. This fix essentially means we're back
to not really being able to handle VPT instructions when tail
predicating.

Differential Revision: https://reviews.llvm.org/D87610
2020-09-16 11:59:29 +01:00
Sam Parker
5953b93f6b [ARM] Add more validForTailPredication
Modify the unit test to inspect all MVE instructions and mark the
load/store/move of vpr/p0 as valid, as well as the remaining scalar
shifts.

Differential Revision: https://reviews.llvm.org/D87753
2020-09-16 11:51:50 +01:00
Simon Pilgrim
6d100e4f64 [DAG] Remover getOperand() call. NFCI. 2020-09-16 11:18:58 +01:00
Sam Tebbs
44c6b51e9c [ARM][LowOverheadLoops] Fix tests after ef0b9f3
ef0b9f3 didn't update the tests that it affected.
2020-09-16 11:01:21 +01:00
Georgii Rymar
32405053ae [llvm-readobj][test] - Improve section-symbols.test
`section-symbols.test` tests how we print section symbols in
different situations.

We might have 2 different cases:
1) A named STT_SECTION symbol.
2) An unnamed STT_SECTION symbol.

Usually section symbols have no name and then `--symbols` uses their
section names when prints them. If symbol has a name, then it is used.

For `--relocations` we also want to have this logic probably,
but currently we always ignore symbol names and always use section names.
It is not consistent with GNU readelf and with our logic for `--symbols`.

This patch refines testing to document the existent behavior and improve
coverage.

Differential revision: https://reviews.llvm.org/D87612
2020-09-16 12:36:09 +03:00
Andrew Ng
dc5cf0feeb [Support] Add GlobPattern::isTrivialMatchAll()
GlobPattern::isTrivialMatchAll() returns true for the GlobPattern "*"
which will match all inputs.

This can be used to avoid performing expensive preparation of the input
for match() when the result of the match will always be true.

Differential Revision: https://reviews.llvm.org/D87468
2020-09-16 10:26:11 +01:00
Georgii Rymar
314b01deec [llvm-readobj][test] - Address a forgotten review comment for D86923.
Seems I've forgot to address this bit and this looks like a reason
of a failture on mac (http://45.33.8.238/mac/20491/step_11.txt).
2020-09-16 11:51:26 +03:00
Alok Kumar Sharma
fa3e899034 [DebugInfo][flang] DISubrange support for fortran assumed size array
This is needed to support assumed size array of fortran which can have missing upperBound/count
, contrary to current DISubrange support.
Example:
subroutine sub (array1, array2)
  integer :: array1 (*)
  integer :: array2 (4:9, 10:*)

  array1(7:8) = 9
  array2(5, 10) = 10
end subroutine
Now the validation check is relaxed for fortran.

Reviewed By: aprantl

Differential Revision: https://reviews.llvm.org/D87500
2020-09-16 14:15:53 +05:30
Sjoerd Meijer
47d7efbc1f Follow up rG635b87511ec3: forgot to add/commit the new test file. NFC. 2020-09-16 09:38:37 +01:00
Sam Tebbs
d6e34a1a34 [ARM][LowOverheadLoops] Combine a VCMP and VPST into a VPT
This patch combines a VCMP followed by a VPST into a VPT, which has the
same semantics as the combination of the former two.
2020-09-16 09:27:10 +01:00
Yvan Roux
921c5ae39b [ARM][MachineOutliner] Add calls handling.
Handles calls inside outlined regions, by saving and restoring the link
register.

Differential Revision: https://reviews.llvm.org/D87136
2020-09-16 09:54:26 +02:00
Max Kazantsev
b8d7909de9 [Test] Add positive range checks tests in addition to negative 2020-09-16 14:24:42 +07:00
Max Kazantsev
2390eb6a63 [Test] Some more potential range check elimination opportunities 2020-09-16 14:00:19 +07:00
Alina Sbirlea
c911d0caf7 [MemorySSA] Report unoptimized as None, not MayAlias. 2020-09-15 23:58:53 -07:00
Xing GUO
db83a6f653 [obj2yaml] Add support for dumping the .debug_addr(v5) section.
This patch adds support for dumping the .debug_addr(v5) section to
obj2yaml.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D87601
2020-09-16 14:48:03 +08:00
Martin Storsjö
2b119dcf7e [llvm-rc] Lowercase the option definitions. NFC.
This matches how such options are most commonly defined in other tools.

This was pointed out in an earlier review a few months ago, that
the llvm-rc td entries felt shouty.

The INCLUDE option is renamed to includepath, to avoid clashing with
the tablegen include directive.
2020-09-16 09:34:26 +03:00
Martin Storsjö
7b4e9362ee [llvm-rc] Update a comment. NFC.
Fix a typo and mention one missing step.
2020-09-16 09:34:26 +03:00
Martin Storsjö
50a529e27d [llvm-rc] Allow omitting components from VERSIONINFO versions
MS rc.exe doesn't require specifying all 4 components.

Differential Revision: https://reviews.llvm.org/D87570
2020-09-16 09:34:26 +03:00
Alina Sbirlea
3b2eea568d [MemorySSA] Set MustDominate to true for PhiTranslation. 2020-09-15 23:29:57 -07:00
Craig Topper
acde6e65a0 [X86] Don't scalarize gather/scatters with non-power of 2 element counts. Widen instead.
We can pad the mask with zeros in order to widen. We already do
this for power 2 types that are smaller than a legal type.
2020-09-15 23:22:53 -07:00
Craig Topper
1eb43a5d55 [X86] Add test case for non-power of 2 scatter. NFC 2020-09-15 23:03:39 -07:00
Max Kazantsev
67567b8db5 [Test] Add signed version of a test 2020-09-16 11:30:21 +07:00
Serguei Katkov
4f6cfebd9e [InstCombine] Add tests for statepoint simplification
This tests increase coverage for change introduced in D85959

Reviewers: reames, reames
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D87224
2020-09-16 10:56:38 +07:00
Arthur Eubanks
8e54da3615 [NewPM] Fix opt-hot-cold-split.ll under NPM
Pin to legacy PM, there are already NPM RUN lines.
2020-09-15 20:29:20 -07:00
Arthur Eubanks
623ad434a7 [NewPM][SCEV] Fix constant-fold-gep.ll under NPM 2020-09-15 20:25:35 -07:00
Arthur Eubanks
dd08b528d1 [NewPM] Fix 2003-02-19-LoopInfoNestingBug.ll under NPM
Also move it to a more appropriate directory.
2020-09-15 20:21:45 -07:00
Craig Topper
16cd8d4cc5 [X86] Always use 16-bit displacement in 16-bit mode when there is no base or index register.
Previously we only did this if the immediate fit in 16 bits, but
the GNU assembler seems to just truncate.

Fixes PR46952
2020-09-15 19:31:48 -07:00
Alina Sbirlea
29208e15c0 Fix test after D86156. 2020-09-15 19:13:39 -07:00
Krzysztof Parzyszek
718a375cea [Hexagon] Replace incorrect pattern for vpackl HWI32 -> HVi8
V6_vdealb4w is not correct for pairs, use V6_vpackeh/V6_vpackeb instead.
2020-09-15 20:34:50 -05:00