Jim Grosbach
d5e74991f0
Shuffle ARM assembly tests a bit.
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llvm-svn: 135095
2011-07-13 22:19:10 +00:00
Jim Grosbach
fd2ebb4552
Range checking for CDP[2] immediates.
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llvm-svn: 135092
2011-07-13 22:01:08 +00:00
Jim Grosbach
c7e0941dac
Testcases for ARM assembly BX/BXJ instructions.
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llvm-svn: 135078
2011-07-13 20:25:46 +00:00
Jim Grosbach
0313701671
Testcases for ARM assembly BLX/BL instructions.
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llvm-svn: 135072
2011-07-13 20:11:04 +00:00
Jim Grosbach
0caa098513
Range checking for 16-bit immediates in ARM assembly.
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llvm-svn: 135071
2011-07-13 20:10:10 +00:00
Jim Grosbach
9e021b5281
Add tests for ARM parsing of 'BKPT' instruction.
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llvm-svn: 135063
2011-07-13 19:17:36 +00:00
Jim Grosbach
ce9b6636b3
Fix copy-pasto.
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llvm-svn: 135062
2011-07-13 19:16:30 +00:00
Jim Grosbach
9d1a4de9e6
Add tests for ARM parsing of 'BIC' instruction.
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llvm-svn: 135061
2011-07-13 19:12:32 +00:00
Jim Grosbach
7aea4b177f
Add some FIXMEs.
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Keeping the instructions in alphabetical order, just like in the ARM ARM.
Adding FIXMEs for skipped instructions when adding tests out of order.
llvm-svn: 135060
2011-07-13 19:10:23 +00:00
Jim Grosbach
9b9604762e
Add tests for ARM parsing of 'AND' instruction.
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llvm-svn: 135056
2011-07-13 18:55:14 +00:00
Jim Grosbach
a0a947a8ca
Add tests for ARM parsing of 'ADD' instruction
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llvm-svn: 135053
2011-07-13 18:12:46 +00:00
Jim Grosbach
7dbb39dffa
Destination register operand is optional for ADC and SBC ARM.
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llvm-svn: 135052
2011-07-13 17:57:17 +00:00
Jim Grosbach
5db1296fcd
Flesh out ARM Parser support for shifted-register operands.
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Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.
llvm-svn: 135049
2011-07-13 17:50:29 +00:00
Jim Grosbach
295e53b228
Add check for predicate w/o S bit.
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llvm-svn: 134987
2011-07-12 16:25:04 +00:00
Jim Grosbach
fae61bb435
Fix recognition of ARM 'adcs' mnemonic.
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The 'CS' is not a predication suffix in this case.
llvm-svn: 134903
2011-07-11 17:09:57 +00:00
