RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-27 14:02:50 +01:00
Code Issues Projects Releases Wiki Activity
64,439 Commits 4 Branches 5 Tags 704 MiB
a74c787dc8
Commit Graph

15210 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
a74c787dc8 Minor change. Fix comments and remove unused and redundant code 
llvm-svn: 113378
 2010-09-08 18:12:31 +00:00
Bruno Cardoso Lopes
892c337123 x86 vector shuffle lowering now relies only on target specific 
nodes to emit shuffles and don't do isel mask matching anymore.
- Add the selection of the remaining shuffle opcode (movddup)
- Introduce two new functions to "recognize" where we may get
potential folds and add several comments to them explaining why
they are not yet in the desidered shape.
- Add more patterns to fallback the case where we select
a specific shuffle opcode as if it could fold a load, but it
can't, so remap to a valid instruction.
- Add a couple of FIXMEs to address in the following days once
there's a good solution to the current folding problem.

llvm-svn: 113369
 2010-09-08 17:43:25 +00:00
Jim Grosbach
273fed4827 Be more careful about when to do dynamic stack realignment. Since we have an 
option to disable base pointer usage, pay attention to it when deciding
if we can realign (if no base pointer and VLAs, we can't).

llvm-svn: 113366
 2010-09-08 17:22:12 +00:00
Jim Grosbach
5411e69cbd Add missing assert 
llvm-svn: 113365
 2010-09-08 17:05:45 +00:00
Kalle Raiskila
be22226628 Fix CellSPU vector shuffles, again. 
Some cases of lowering to rotate were miscompiled.

llvm-svn: 113355
 2010-09-08 11:53:38 +00:00
Chris Lattner
4e8c89174f add support for the commuted form of the test instruction, rdar://8018260. 
llvm-svn: 113352
 2010-09-08 05:51:12 +00:00
Chris Lattner
752daa9624 implement proper support for sysret{,l,q}, rdar://8403907 
llvm-svn: 113350
 2010-09-08 05:45:34 +00:00
Chris Lattner
40f9f0fdba implement the iret suite of instructions properly, 
fixing rdar://8403974

llvm-svn: 113349
 2010-09-08 05:38:31 +00:00
Chris Lattner
05818145f8 add support for instruction prefixes on the same line as the instruction, 
implementing rdar://8033482 and PR7254.

llvm-svn: 113348
 2010-09-08 05:17:37 +00:00
Chris Lattner
0e0f9094e9 change the MC "ParseInstruction" interface to make it the 
implementation's job to check for and lex the EndOfStatement
marker.

llvm-svn: 113347
 2010-09-08 05:10:46 +00:00
Chris Lattner
7435beb421 gas accepts xchg <mem>, <reg> as a synonym for xchg <reg>, <mem>. 
Add this to the mc assembler, fixing PR8061

llvm-svn: 113346
 2010-09-08 04:53:27 +00:00
NAKAMURA Takumi
e223d51276 ARM/Disassembler: Fix definitions incompatible(unsigned and uint32_t) to Cygwin-1.5, following up to r113255. 
llvm-svn: 113345
 2010-09-08 04:48:17 +00:00
Chris Lattner
8f621d5039 fix the encoding of the "jump on *cx" family of instructions, 
rdar://8061602

llvm-svn: 113343
 2010-09-08 04:30:51 +00:00
Jim Grosbach
6aba2dc40a remove trailing whitespace 
llvm-svn: 113338
 2010-09-08 03:54:02 +00:00
Jim Grosbach
9e69f92835 remove obsolete comment 
llvm-svn: 113337
 2010-09-08 03:51:44 +00:00
Jim Grosbach
7a957dc761 disable for the moment while tracking down a few Thumb2-O0 failure that look 
related. (attempt deux, complete w/ test update this time)

llvm-svn: 113333
 2010-09-08 02:00:34 +00:00
Jim Grosbach
31f79e5d47 woops. need to update a test along with this. 
llvm-svn: 113332
 2010-09-08 01:49:09 +00:00
Jim Grosbach
89098087dd disable temporarily while sorting out a few test failures in Thumb2-O0 tests. 
llvm-svn: 113331
 2010-09-08 01:47:49 +00:00
Jim Grosbach
e1ea3730f4 correct spill code to properly determine if dynamic stack realignment is 
present in the function and thus whether aligned load/store instructions can
be used.

llvm-svn: 113323
 2010-09-08 00:26:59 +00:00
Jim Grosbach
27a5b1fd3b VFP/NEON load/store multiple instructions are addrmode4, not 5. 
llvm-svn: 113322
 2010-09-08 00:25:50 +00:00
Jim Grosbach
5d310ec4a5 To shrink a t2LDM instruction to the 16-bit wide tLDM instruction, the base 
register must be one of the destination registers for the load. Otherwise,
the tLDM instruction will write-back to the base register, which isn't what's
desired (otherwise, we'd have a t2LDM_UPD instead).

rdar://8394087

llvm-svn: 113297
 2010-09-07 22:30:53 +00:00
Jim Grosbach
b40371d3bf grammar tweak 
llvm-svn: 113289
 2010-09-07 21:30:25 +00:00
Bruno Cardoso Lopes
a4ca8c3ac5 Factor out some x86 vector shuffle rewriting and add comments about the direction the shuffle lowering is heading to 
llvm-svn: 113286
 2010-09-07 21:03:14 +00:00
Bruno Cardoso Lopes
e33983dba9 Move code around to prepare for moving some of the logic together to another function 
llvm-svn: 113267
 2010-09-07 20:20:27 +00:00
Bill Wendling
9bb7ac566f Add an MVT::x86mmx type. It will take the place of all current MMX vector types. 
llvm-svn: 113261
 2010-09-07 20:03:56 +00:00
Evan Cheng
5a058ed2a0 Remove a dead comment. 
llvm-svn: 113259
 2010-09-07 20:01:10 +00:00
Chris Lattner
7b50cefea8 hopefully fix a problem building on cygwin-1.5 
llvm-svn: 113255
 2010-09-07 19:50:53 +00:00
Bruno Cardoso Lopes
21e1fc67c3 decouple MMX check from regular splat checks. Some refactoring is coming, and MMX should be left alone to be easily removed after moving to intrinsics 
llvm-svn: 113247
 2010-09-07 18:41:45 +00:00
Bruno Cardoso Lopes
dcc8690051 Remove now useless check, because the code can be matched below, no need to leave it for isel 
llvm-svn: 113242
 2010-09-07 18:29:03 +00:00
Bruno Cardoso Lopes
e6f7e4684d Minor change. Since the checks are equivalent, use isMMX 
llvm-svn: 113239
 2010-09-07 18:24:00 +00:00
Nick Lewycky
cad1395824 Create PTX backend. Patch by Che-Liang Chiou! 
llvm-svn: 113235
 2010-09-07 18:14:24 +00:00
Dale Johannesen
8354cab2de Add patterns for MMX that use the new intrinsics. 
Enable palignr intrinsic.
These may need adjustment for a new VT in due course.

llvm-svn: 113233
 2010-09-07 18:10:56 +00:00
Bruno Cardoso Lopes
92bb02f722 Remove unused target specific node 
llvm-svn: 113224
 2010-09-07 17:38:55 +00:00
Benjamin Kramer
32f7af702a Don't leak the old operand when transforming "sldt" into "sldtw". 
llvm-svn: 113200
 2010-09-07 14:40:58 +00:00
Chris Lattner
fd65cfd3eb add missing cmov aliases, this resolves rdar://8208499 
llvm-svn: 113189
 2010-09-07 00:05:45 +00:00
Chris Lattner
927dc7a5d2 remove duplicated entry 
llvm-svn: 113188
 2010-09-06 23:57:24 +00:00
Chris Lattner
5a696fb3ca "sldt <mem>" is ambiguous in 64-bit mode, but should 
always be disambiguated as sldtw.  sldtw and sldtq with
a mem operands have the same effect, but sldtw is more
compact.  Force it to sldtw, resolving rdar://8017530

llvm-svn: 113186
 2010-09-06 23:51:44 +00:00
Chris Lattner
3377802111 fix rdar://8017621 - llvm-mc can't guess encoding for "push $(1000)" 
llvm-svn: 113184
 2010-09-06 23:40:56 +00:00
Chris Lattner
6ecbbff857 fix the operand constraints of the immediate form of in/out, 
allowing unsigned 8-bit operands.  This fixes rdar://8208481

llvm-svn: 113182
 2010-09-06 23:29:05 +00:00
Chris Lattner
6bfa0d9988 in the case where an instruction only has one implementation 
of a mneumonic, report operand errors with better location
info.  For example, we now report:

t.s:6:14: error: invalid operand for instruction
        cwtl $1
             ^

but we fail for common cases like:

t.s:11:4: error: invalid operand for instruction
   addl $1, $1
   ^

because we don't know if this is supposed to be the reg/imm or imm/reg
form.

llvm-svn: 113178
 2010-09-06 22:11:18 +00:00
Chris Lattner
bb5e19cb63 Now that we know if we had a total fail on the instruction mnemonic, 
give a more detailed error.  Before:

t.s:11:4: error: unrecognized instruction
   addl $1, $1
   ^
t.s:12:4: error: unrecognized instruction
   f2efqefa $1
   ^

After:

t.s:11:4: error: invalid operand for instruction
   addl $1, $1
   ^
t.s:12:4: error: invalid instruction mnemonic 'f2efqefa'
   f2efqefa $1
   ^

This fixes rdar://8017912 - llvm-mc says "unrecognized instruction" when it means "invalid operands"

llvm-svn: 113176
 2010-09-06 21:54:15 +00:00
Chris Lattner
87234fd589 simplify the hacks around jrcxz. 
llvm-svn: 113167
 2010-09-06 20:10:12 +00:00
Chris Lattner
68f7c5b750 have tblgen detect when an instruction would have matched, but 
failed because a subtarget feature was not enabled.  Use this to
remove a bunch of hacks from the X86AsmParser for rejecting things
like popfl in 64-bit mode.  Previously these hacks weren't needed,
but were important to get a message better than "invalid instruction"
when used in the wrong mode.

This also fixes bugs where pushal would not be rejected correctly in
32-bit mode (just pusha).

llvm-svn: 113166
 2010-09-06 20:08:02 +00:00
Chris Lattner
22bb9cb511 change MatchInstructionImpl to return an enum instead of bool. 
llvm-svn: 113165
 2010-09-06 19:22:17 +00:00
Chris Lattner
45a204be76 have AsmMatcherEmitter.cpp produce the hunk of code that gets included 
into the middle of the class, and rework how the different sections of
the generated file are conditionally included for simplicity.

llvm-svn: 113163
 2010-09-06 19:11:01 +00:00
Roman Divacky
f760edb301 Redefine LOOP* instructions from I to Ii8PCRel as they take an i8 argument. 
llvm-svn: 113158
 2010-09-06 18:43:14 +00:00
Chris Lattner
3bd0996c77 random cleanups 
llvm-svn: 113157
 2010-09-06 18:32:06 +00:00
Chris Lattner
c0e5368884 remove some dead code. t2addrmode_imm8s4 is never used in a 
pattern, so there is no need to define a matching function.

llvm-svn: 113122
 2010-09-05 22:51:11 +00:00
Chris Lattner
bd47c48735 cleanups. 
llvm-svn: 113119
 2010-09-05 21:18:45 +00:00
Chris Lattner
908d8e9de2 update this. 
llvm-svn: 113116
 2010-09-05 20:22:09 +00:00