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Commit Graph

725 Commits

Author SHA1 Message Date
Akira Hatanaka
44c745931f Add pattern used to match MipsLo, which is needed when the instruction selector
tries to match a dead MipsLo node (explanation in the link below).

http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead

llvm-svn: 139634
2011-09-13 20:13:58 +00:00
Akira Hatanaka
052c83e7a2 Support for PSP is gone too.
llvm-svn: 139622
2011-09-13 18:55:33 +00:00
Akira Hatanaka
4cdd5fca36 It is not necessary to search for mipsallegrex in target triple string.
llvm-svn: 139607
2011-09-13 17:35:28 +00:00
Akira Hatanaka
45bb471537 O64 will not be supported.
llvm-svn: 139421
2011-09-09 22:22:48 +00:00
Akira Hatanaka
da477aa5eb Make F31 and D15 non-reserved registers.
llvm-svn: 139420
2011-09-09 22:11:26 +00:00
Akira Hatanaka
be07ce941b Mips32 does not reserve even-numbered floating point registers.
llvm-svn: 139412
2011-09-09 21:31:46 +00:00
Akira Hatanaka
f65d050693 Drop support for Mips1 and Mips2.
llvm-svn: 139405
2011-09-09 20:45:50 +00:00
Akira Hatanaka
17df2dfe8c Drop support for Allegrex. Allegrex implements a variant of Mips2.
llvm-svn: 139383
2011-09-09 19:00:51 +00:00
Akira Hatanaka
e1eb015eb9 Change default target architecture from Mips1 to Mips32r1 in preparation for
removing support for Mips1 and Mips2. 

This change and the ones that follow have been discussed with and approved by
Bruno.

llvm-svn: 139344
2011-09-09 01:13:27 +00:00
Akira Hatanaka
94deb5f3f9 80 columns.
llvm-svn: 139339
2011-09-09 00:13:35 +00:00
James Molloy
f781d3d8e9 Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.
llvm-svn: 139237
2011-09-07 17:24:38 +00:00
Duncan Sands
d1311488fe Add codegen support for vector select (in the IR this means a select
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons.  Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all").  Patch mostly by
Nadav Rotem.

llvm-svn: 139159
2011-09-06 19:07:46 +00:00
Akira Hatanaka
6617606549 Fix typo. Patch by Liu.
llvm-svn: 138866
2011-08-31 17:49:04 +00:00
James Molloy
e841c9709a Fix typo in MipsMCTargetDesc.h; Patch supplied by Liu (proljc@gmail.com)
llvm-svn: 138796
2011-08-30 07:23:29 +00:00
Eli Friedman
6d27cb5e01 Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly.
llvm-svn: 138751
2011-08-29 18:23:02 +00:00
Evan Cheng
420bf5446c Move TargetRegistry and TargetSelect from Target to Support where they belong.
These are strictly utilities for registering targets and components.

llvm-svn: 138450
2011-08-24 18:08:43 +00:00
Evan Cheng
ed13551c1d Some refactoring so TargetRegistry.h no longer has to include any files
from MC.

llvm-svn: 138367
2011-08-23 20:15:21 +00:00
Akira Hatanaka
02cff5ae2d Fix bug in function IsShiftedMask. Remove parameter SizeInBits, which is not
needed for Mips32.

llvm-svn: 138132
2011-08-19 22:59:00 +00:00
Akira Hatanaka
163382894e Use subword loads instead of a 4-byte load when the size of a structure (or a
piece of it) that is being passed by value is smaller than a word.

llvm-svn: 138007
2011-08-18 23:39:37 +00:00
Akira Hatanaka
1876aadea7 Make IsShiftedMask a static function rather than defining it in an
anonymous namespace.

llvm-svn: 137975
2011-08-18 20:07:42 +00:00
Bruno Cardoso Lopes
19359daff9 Clenup and fix encoding for Mips ins and ext instruction
llvm-svn: 137943
2011-08-18 16:30:49 +00:00
Akira Hatanaka
0af1edcce0 Changed definition of EXT and INS per Bruno's comments.
llvm-svn: 137892
2011-08-17 22:59:46 +00:00
Akira Hatanaka
6eb513003d Add support for half-word unaligned loads and stores.
llvm-svn: 137848
2011-08-17 18:49:18 +00:00
Akira Hatanaka
60ccc76576 Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment.
llvm-svn: 137831
2011-08-17 17:45:08 +00:00
Akira Hatanaka
0179c7fa68 Add support for ext and ins.
llvm-svn: 137804
2011-08-17 02:05:42 +00:00
Akira Hatanaka
12df91513e Fix handling of double precision loads and stores when Mips1 is targeted.
Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This 
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same 
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.

llvm-svn: 137711
2011-08-16 03:51:51 +00:00
Akira Hatanaka
d8865ea155 Define function MipsMCInstLower::LowerOperand.
llvm-svn: 137707
2011-08-16 02:21:03 +00:00
Akira Hatanaka
1e1909b7c8 Add parameter Offset to MipsMCInstLower::LowerSymbolOperand.
llvm-svn: 137706
2011-08-16 02:15:03 +00:00
Akira Hatanaka
c9c0190cbe Define unaligned load and store.
llvm-svn: 137515
2011-08-12 21:30:06 +00:00
Akira Hatanaka
5706262bc2 When constant double 0.0 is lowered, make sure 0 is copied directly from an
integer register to a floating point register. It is not valid to interpret
the value of a floating pointer register as part of a double precision
floating point value after a single precision floating point computational
or move instruction stores its result to the register.

- In the test case, the following code is generated before this patch is
  applied:
mtc1  $zero, $f2    ; unformatted copy to $f2
mov.s $f0, $f2      ; $f0 is in single format
sdc1  $f12, 0($sp)
mov.s $f1, $f2      ; $f1 is in single format
c.eq.d  $f12, $f0   ; $f0 cannot be interpreted as double

- The following code is generated after this patch is applied:
mtc1  $zero, $f0    ; unformatted copy to $f0
mtc1  $zero, $f1    ; unformatted copy to $f1
c.eq.d  $f12, $f0   ; $f0 can be interpreted as double

Bhanu Chetlapalli and Chris Dearman at MIPS technologies reported this bug and
provided the test case.

llvm-svn: 137484
2011-08-12 18:09:59 +00:00
Akira Hatanaka
b787f8a8a5 Enclose directive .cprestore with .set macro and nomacro to silence assembler
warning. 

llvm-svn: 137378
2011-08-11 22:42:31 +00:00
Akira Hatanaka
e8e203f116 Add isIndirectBranch flag.
llvm-svn: 137351
2011-08-11 21:05:37 +00:00
Eli Friedman
afd08dcc2c New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing.
I think this completes the basic CodeGen for atomicrmw and cmpxchg.

llvm-svn: 136813
2011-08-03 21:06:02 +00:00
Chandler Carruth
38c8c22382 Actually finish switching to the new system for Target sublibrary
TableGen deps introduced in r136023. This completes the fixing that
dgregor started in r136621. Sorry for missing these the first time
around.

This should fix some of the random race-condition failures people are
still seeing with CMake.

llvm-svn: 136643
2011-08-01 19:55:11 +00:00
Chandler Carruth
f7890e34b9 Rewrite the CMake build to use explicit dependencies between libraries,
specified in the same file that the library itself is created. This is
more idiomatic for CMake builds, and also allows us to correctly specify
dependencies that are missed due to bugs in the GenLibDeps perl script,
or change from compiler to compiler. On Linux, this returns CMake to
a place where it can relably rebuild several targets of LLVM.

I have tried not to change the dependencies from the ones in the current
auto-generated file. The only places I've really diverged are in places
where I was seeing link failures, and added a dependency. The goal of
this patch is not to start changing the dependencies, merely to move
them into the correct location, and an explicit form that we can control
and change when necessary.

This also removes a serialization point in the build because we don't
have to scan all the libraries before we begin building various tools.
We no longer have a step of the build that regenerates a file inside the
source tree. A few other associated cleanups fall out of this.

This isn't really finished yet though. After talking to dgregor he urged
switching to a single CMake macro to construct libraries with both
sources and dependencies in the arguments. Migrating from the two macros
to that style will be a follow-up patch.

Also, llvm-config is still generated with GenLibDeps.pl, which means it
still has slightly buggy dependencies. The internal CMake
'llvm-config-like' macro uses the correct explicitly specified
dependencies however. A future patch will switch llvm-config generation
(when using CMake) to be based on these deps as well.

This may well break Windows. I'm getting a machine set up now to dig
into any failures there. If anyone can chime in with problems they see
or ideas of how to solve them for Windows, much appreciated.

llvm-svn: 136433
2011-07-29 00:14:25 +00:00
Oscar Fuentes
af4fae1c0f Explicitly declare a library dependency of LLVM*Desc to
LLVM*AsmPrinter.

GenLibDeps.pl fails to detect vtable references. As this is the only
referenced symbol from LLVM*Desc to LLVM*AsmPrinter on optimized
builds, the algorithm that creates the list of libraries to be linked
into tools doesn't know about the dependency and sometimes places the
libraries on the wrong order, yielding error messages like this:

../../lib/libLLVMARMDesc.a(ARMMCTargetDesc.cpp.o): In function
`llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo const&)':
ARMMCTargetDesc.cpp:(.text._ZN4llvm14ARMInstPrinterC1ERKNS_9MCAsmInfoE
[llvm::ARMInstPrinter::ARMInstPrinter(llvm::MCAsmInfo
const&)]+0x2a): undefined reference to `vtable for
llvm::ARMInstPrinter'

llvm-svn: 136328
2011-07-28 02:33:52 +00:00
Eli Friedman
842ea169de Code generation for 'fence' instruction.
llvm-svn: 136283
2011-07-27 22:21:52 +00:00
Chandler Carruth
a571c5d5d3 Clean up a pile of hacks in our CMake build relating to TableGen.
The first problem to fix is to stop creating synthetic *Table_gen
targets next to all of the LLVM libraries. These had no real effect as
CMake specifies that add_custom_command(OUTPUT ...) directives (what the
'tablegen(...)' stuff expands to) are implicitly added as dependencies
to all the rules in that CMakeLists.txt.

These synthetic rules started to cause problems as we started more and
more heavily using tablegen files from *subdirectories* of the one where
they were generated. Within those directories, the set of tablegen
outputs was still available and so these synthetic rules added them as
dependencies of those subdirectories. However, they were no longer
properly associated with the custom command to generate them. Most of
the time this "just worked" because something would get to the parent
directory first, and run tablegen there. Once run, the files existed and
the build proceeded happily. However, as more and more subdirectories
have started using this, the probability of this failing to happen has
increased. Recently with the MC refactorings, it became quite common for
me when touching a large enough number of targets.

To add insult to injury, several of the backends *tried* to fix this by
adding explicit dependencies back to the parent directory's tablegen
rules, but those dependencies didn't work as expected -- they weren't
forming a linear chain, they were adding another thread in the race.

This patch removes these synthetic rules completely, and adds a much
simpler function to declare explicitly that a collection of tablegen'ed
files are referenced by other libraries. From that, we can add explicit
dependencies from the smaller libraries (such as every architectures
Desc library) on this and correctly form a linear sequence. All of the
backends are updated to use it, sometimes replacing the existing attempt
at adding a dependency, sometimes adding a previously missing dependency
edge.

Please let me know if this causes any problems, but it fixes a rather
persistent and problematic source of build flakiness on our end.

llvm-svn: 136023
2011-07-26 00:09:08 +00:00
Evan Cheng
040076bda2 Separate MCInstPrinter registration from AsmPrinter registration.
llvm-svn: 135974
2011-07-25 21:20:24 +00:00
Evan Cheng
f2dd840123 createXXXMCCodeGenInfo should be static.
llvm-svn: 135826
2011-07-23 00:01:04 +00:00
Evan Cheng
7b4cb12a95 Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo,
InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC.

llvm-svn: 135812
2011-07-22 21:58:54 +00:00
Oscar Fuentes
c951cb1ef4 Fix CMake build
llvm-svn: 135698
2011-07-21 19:10:57 +00:00
Bruno Cardoso Lopes
6934331f4c Added the infrastructute necessary for MIPS JIT support. Patch by Vladimir
Stefanovic. I removed the part that actually emits the instructions cause
I want that to get in better shape first and in incremental steps. This
also makes it easier to review the upcoming parts.

llvm-svn: 135678
2011-07-21 16:28:51 +00:00
Evan Cheng
55d7fcc5f7 - Move CodeModel from a TargetMachine global option to MCCodeGenInfo.
- Introduce JITDefault code model. This tells targets to set different default
  code model for JIT. This eliminates the ugly hack in TargetMachine where
  code model is changed after construction.

llvm-svn: 135580
2011-07-20 07:51:56 +00:00
Akira Hatanaka
a9cbfe8f88 Change name of class.
llvm-svn: 135550
2011-07-20 00:53:09 +00:00
Akira Hatanaka
f61c905927 Define classes for definitions of atomic instructions.
llvm-svn: 135546
2011-07-20 00:23:01 +00:00
Akira Hatanaka
a50bbdfe15 Lower memory barriers to sync instructions.
llvm-svn: 135537
2011-07-19 23:30:50 +00:00
Akira Hatanaka
cccc5fca34 Change variable name.
llvm-svn: 135522
2011-07-19 20:56:53 +00:00
Akira Hatanaka
14e517df43 Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or
ANDi, when the instruction does not have any immediate operands.

llvm-svn: 135520
2011-07-19 20:34:00 +00:00
Akira Hatanaka
b4db39fa83 Use descriptive variable names.
llvm-svn: 135514
2011-07-19 20:11:17 +00:00