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23 Commits

Author SHA1 Message Date
Daniel Dunbar
1dd74c37c5 X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same 
instruction, we only want to allow the one for the current subtarget.
 - This also fixes suffix matching for jmp instructions, because it eliminates
   the ambiguity between 'jmpl' and 'jmpq'.

llvm-svn: 108746
 2010-07-19 20:44:16 +00:00
Daniel Dunbar
3b0ff3bac3 MC/X86: We now match instructions like "incl %eax" correctly for the arch we are 
assembling; remove crufty custom cleanup code.

llvm-svn: 108681
 2010-07-19 06:14:54 +00:00
Chris Lattner
ed5a217085 fix rdar://7873482 by teaching the instruction encoder to emit 
segment prefixes.  Daniel wrote most of this patch.

llvm-svn: 106364
 2010-06-19 00:34:00 +00:00
Kevin Enderby
fbd982b12f MC/X86: Add alias for movzx. 
llvm-svn: 105005
 2010-05-28 21:20:21 +00:00
Kevin Enderby
e336aaa32b The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is required 
for the 64-bit version of the Bit Test instruction.

llvm-svn: 104621
 2010-05-25 18:16:58 +00:00
Daniel Dunbar
7c60f7caa2 MC/X86: Add alias for setz, setnz, jz, jnz. 
llvm-svn: 104435
 2010-05-22 06:37:33 +00:00
Kevin Enderby
1e4a4f5899 Added retl for 32-bit x86 and added retq for 64-bit x86. 
llvm-svn: 104394
 2010-05-21 23:01:38 +00:00
Daniel Dunbar
3a0c98ca87 MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq. 
llvm-svn: 104275
 2010-05-20 20:36:29 +00:00
Dan Gohman
c8b4555a94 Fix assembly parsing and encoding of the pushf and popf family of 
instructions.

llvm-svn: 104231
 2010-05-20 16:16:00 +00:00
Chris Lattner
887e8f9f53 reapply r103668 with a fix. Never make "minor syntax changes" 
after testing before committing.

llvm-svn: 103681
 2010-05-13 00:02:47 +00:00
Chris Lattner
361c115f23 revert r103668 for now, it is apparently breaking things. 
llvm-svn: 103677
 2010-05-12 23:40:59 +00:00
Chris Lattner
91a836a9c7 moffset forms of moves are x86-32 only, make the parser 
lower them to the correct x86-64 instructions since we 
don't have a clean way to handle this in td files yet.
rdar://7947184

llvm-svn: 103668
 2010-05-12 23:13:36 +00:00
Chris Lattner
c788971da7 fix rdar://7947167 - llvm-mc doesn't match movsq 
llvm-svn: 103199
 2010-05-06 21:48:14 +00:00
Daniel Dunbar
f803121396 MC/X86: Rename alternate spellings of {ADD64,CMP64} and mark as "code gen only" so they don't get selected by the asm matcher. 
llvm-svn: 98972
 2010-03-19 18:07:48 +00:00
Daniel Dunbar
3ef39d497f X86: Fix encoding for TEST64rr. 
llvm-svn: 98919
 2010-03-19 01:15:03 +00:00
Daniel Dunbar
1a50b05aff X86MCCodeEmitter: Fix two minor issues with reloc_riprel_4byte_movq_load, we 
were missing it on some movq instructions and were not including the appropriate
PCrel bias.

llvm-svn: 98880
 2010-03-18 21:53:54 +00:00
Chris Lattner
bf3e096258 fix an x86-64 encoding bug Daniel found. 
llvm-svn: 98855
 2010-03-18 20:04:36 +00:00
Chris Lattner
45ab55ccec add a special relocation type for movq loads for object 
files that produce special relocation types where the 
linker changes movq's into lea's.

llvm-svn: 98839
 2010-03-18 18:10:56 +00:00
Daniel Dunbar
a6526284f4 X86: Fix ADD64i32 encoding. 
llvm-svn: 98457
 2010-03-13 22:49:39 +00:00
Chris Lattner
b29b154904 make pcrel immediate values relative to the start of the field, 
not the end of the field, fixing rdar://7651978

llvm-svn: 96330
 2010-02-16 05:03:17 +00:00
Chris Lattner
d4fe983f23 rip out the 'heinous' x86 MCCodeEmitter implementation. 
We still have the templated X86 JIT emitter, *and* the
almost-copy in X86InstrInfo for getting instruction sizes.

llvm-svn: 96059
 2010-02-13 00:49:29 +00:00
Daniel Dunbar
4ef0be5df5 MC/X86: Push immediate operands as immediates not expressions when possible. 
llvm-svn: 96055
 2010-02-13 00:17:21 +00:00
Chris Lattner
4170bb81da implement the rest of correct x86-64 encoder support for 
rip-relative addresses, and add a testcase.

llvm-svn: 96040
 2010-02-12 23:24:09 +00:00