Evan Cheng
b44d480808
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP
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pipeline forwarding path.
llvm-svn: 115098
2010-09-29 22:42:35 +00:00
Bob Wilson
eb520cd057
Spelling fix.
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llvm-svn: 113978
2010-09-15 16:28:21 +00:00
Evan Cheng
c9cb37516d
Teach if-converter to be more careful with predicating instructions that would
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take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.
llvm-svn: 113570
2010-09-10 01:29:16 +00:00
Evan Cheng
b79a03a3ca
For each instruction itinerary class, specify the number of micro-ops each
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instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.
This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.
llvm-svn: 113513
2010-09-09 18:18:55 +00:00
Chris Lattner
3fdb8fcaeb
declare a class with 'class' instead of struct to avoid tag mismatch
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warnings, and don't shift by a bool. Patch by Rizky Herucakra!
llvm-svn: 105886
2010-06-12 15:46:56 +00:00
Anton Korobeynikov
f93145e685
Initial support for different kinds of FU reservation.
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llvm-svn: 100645
2010-04-07 18:19:32 +00:00
David Goodwin
3ac3dcacc7
Make the end-of-itinerary mark explicit. Some cleanup.
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llvm-svn: 82709
2009-09-24 20:22:50 +00:00
David Goodwin
9a605efb84
Use the schedule itinerary operand use/def cycle information to adjust dependence edge latency for post-RA scheduling.
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llvm-svn: 79425
2009-08-19 16:08:58 +00:00
David Goodwin
d65007a4a3
Extend the instruction itinerary model to include the ability to indicate the def and use cycle for each operand. This additional information is optional, so existing itineraries do not need to be changed.
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llvm-svn: 79247
2009-08-17 16:02:57 +00:00
David Goodwin
90e7f9873c
Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.
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llvm-svn: 78827
2009-08-12 18:31:53 +00:00
David Goodwin
3245141543
Post RA scheduler changes. Introduce a hazard recognizer that uses the target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets.
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llvm-svn: 78563
2009-08-10 15:55:25 +00:00
Dan Gohman
60693dacec
Implement ComputeLatency for MachineInstr ScheduleDAGs. Factor
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some of the latency computation logic out of the SDNode
ScheduleDAG code into a TargetInstrItineraries helper method
to help with this.
llvm-svn: 59761
2008-11-21 00:12:10 +00:00
Dan Gohman
b8f4f58938
Delete redundant inline keywords.
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llvm-svn: 59754
2008-11-20 22:10:21 +00:00
Dan Gohman
0ba3f17e9f
Doxygenate comments.
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llvm-svn: 59753
2008-11-20 22:09:52 +00:00
Dan Gohman
22002efa15
A quick nm audit turned up several fixed tables and objects that were
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marked read-write. Use const so that they can be allocated in a
read-only segment.
llvm-svn: 48800
2008-03-25 21:45:14 +00:00
Chris Lattner
e0b1ee937a
Don't attribute in file headers anymore. See llvmdev for the
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discussion of this change. Boy are my fingers tired. ;-)
llvm-svn: 45411
2007-12-29 19:59:42 +00:00
Jeff Cohen
16669485c1
<cassert> no longer required to make VC++ happy.
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llvm-svn: 24177
2005-11-04 02:59:16 +00:00
Duraid Madina
feeaabd6f1
change NULL to 0, unbreaks the ppc target when building on ia64
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llvm-svn: 24176
2005-11-04 01:45:04 +00:00
Jim Laskey
42681c1d58
1. Remove ranges from itinerary data.
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2. Tidy up the subtarget emittined code.
llvm-svn: 24172
2005-11-03 22:47:41 +00:00
Jeff Cohen
ae39880d3a
Keep VC++ happy.
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llvm-svn: 24148
2005-11-02 04:03:16 +00:00
Jim Laskey
4cb1e29b27
Allow itineraries to be passed through the Target Machine.
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llvm-svn: 24139
2005-11-01 20:06:59 +00:00
Jim Laskey
03f8b2a366
Structures used to hold scheduling information.
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llvm-svn: 24049
2005-10-27 18:18:05 +00:00
