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Commit Graph

77549 Commits

Author SHA1 Message Date
Benjamin Kramer
c0001c42c6 X86: Emit logical shift by constant splat of <16 x i8> as a <8 x i16> shift and zero out the bits where zeros should've been shifted in.
llvm-svn: 143315
2011-10-30 17:31:21 +00:00
Craig Topper
e77289b243 Fix return type for X86 mpsadbw instrinsic. The instruction takes in a vector of 8-bit integers, but produces a vector of 16-bit integers.
llvm-svn: 143313
2011-10-30 17:22:45 +00:00
Nadav Rotem
8282fc9e3b Fix pr11266.
On x86: (shl V, 1) -> add V,V

Hardware support for vector-shift is sparse and in many cases we scalarize the
result. Additionally, on sandybridge padd is faster than shl.

llvm-svn: 143311
2011-10-30 13:24:22 +00:00
Benjamin Kramer
eb62811647 Silence compiler warning.
llvm-svn: 143308
2011-10-30 08:39:55 +00:00
Nadav Rotem
68400d352b Stabilize the test by specifying an exact cpu target
llvm-svn: 143307
2011-10-30 08:07:50 +00:00
Roman Divacky
c0f49b6277 Update on PPC32.
llvm-svn: 143306
2011-10-30 07:49:04 +00:00
Bill Wendling
c5c8918efc Do a relative path ln command instead of an absolute path one. Some people strangely enough have different directory layouts...
llvm-svn: 143302
2011-10-29 23:49:52 +00:00
NAKAMURA Takumi
ef79c816eb CREDITS.TXT: Add a line. (test commit)
llvm-svn: 143300
2011-10-29 23:42:14 +00:00
Nadav Rotem
6c79131e39 Add a new DAGCombine optimization for BUILD_VECTOR.
If all of the inputs are zero/any_extended, create a new simple BV
which can be further optimized by other BV optimizations.

llvm-svn: 143297
2011-10-29 21:23:04 +00:00
Benjamin Kramer
24c4266ada Force SSE for this test.
llvm-svn: 143291
2011-10-29 19:43:44 +00:00
Benjamin Kramer
7b1acc52c1 PPC: Disable moves for all CR subregisters.
Should fix assertion failures on ppc buildbots.

llvm-svn: 143290
2011-10-29 19:43:38 +00:00
Benjamin Kramer
d32c541fe4 SimplifyLibCalls: Use IRBuilder.CreateGlobalString when creating a string for printf->puts, which correctly sets the unnamed_addr bit on the resulting GlobalVariable.
Fixes PR11264.

llvm-svn: 143289
2011-10-29 19:43:31 +00:00
llvm
ce47648159 Test.
llvm-svn: 143277
2011-10-29 14:16:39 +00:00
Bill Wendling
61e2b39b06 Revise ThreadSanitizer mention so that it lists the correct frontends.
llvm-svn: 143268
2011-10-29 01:11:15 +00:00
Bill Wendling
f102657a93 Add Cling to the External Projects list.
llvm-svn: 143267
2011-10-29 01:10:01 +00:00
Eli Friedman
7c9bef9ba8 Revert r143214; it's breaking a bunch of stuff.
llvm-svn: 143265
2011-10-29 00:56:07 +00:00
Dan Gohman
826cec9a4b Revert r143206, as there are still some failing tests.
llvm-svn: 143262
2011-10-29 00:41:52 +00:00
NAKAMURA Takumi
78a0f170d6 test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll: [PR11218] Mark "REQUIRES: asserts" for now.
llvm-svn: 143247
2011-10-28 23:11:03 +00:00
Jim Grosbach
37119b8a01 ARM mode 'mov' to 'mvn' assembler alias.
llvm-svn: 143237
2011-10-28 22:50:54 +00:00
Jim Grosbach
f3285dba99 Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
  mov r2, #-3
becomes
  mvn r2, #2

rdar://10349224

llvm-svn: 143235
2011-10-28 22:36:30 +00:00
Jim Grosbach
3d628952f6 Allow InstAlias's to use immediate matcher patterns that xform the value.
For example,

On ARM, "mov r3, #-3" is an alias for "mvn r3, #2", so we want to use a
matcher pattern that handles the bitwise negation when mapping to t2MVNi.

llvm-svn: 143233
2011-10-28 22:32:53 +00:00
Owen Anderson
9e033c5b03 Fix illegal disassembly testcase.
llvm-svn: 143231
2011-10-28 21:45:09 +00:00
Jim Grosbach
7a4e1e2e0b Clarify example snippets a bit.
llvm-svn: 143224
2011-10-28 20:52:20 +00:00
Owen Anderson
5fdb303642 Specify that the high bit of the alignment field is fixed to 0 on these instructions.
llvm-svn: 143220
2011-10-28 20:43:24 +00:00
Akira Hatanaka
f71673c585 Make changes necessary in LowerFormalArguments to support Mips64.
llvm-svn: 143218
2011-10-28 19:55:48 +00:00
Akira Hatanaka
3069ec27da Make changes necessary in LowerCall to support Mips64.
llvm-svn: 143217
2011-10-28 19:49:00 +00:00
Duncan Sands
7791a854c3 The expression icmp eq (select (icmp eq x, 0), 1, x), 0 folds to false.
Spotted by my super-optimizer in 186.crafty and 450.soplex.  We really
need a proper infrastructure for handling generalizations of this kind
of thing (which occur a lot), however this case is so simple that I decided
to go ahead and implement it directly.

llvm-svn: 143214
2011-10-28 19:01:20 +00:00
Akira Hatanaka
856f4e30b2 Add variable IsO32 to MipsTargetLowering.
llvm-svn: 143213
2011-10-28 18:47:24 +00:00
Duncan Sands
3483c23658 A shift of a power of two is a power of two or zero.
For completeness - not spotted in the wild.

llvm-svn: 143211
2011-10-28 18:30:05 +00:00
Duncan Sands
5730fe6a31 Fold icmp ugt (udiv X, Y), X to false. Spotted by my super-optimizer
in 186.crafty.

llvm-svn: 143209
2011-10-28 18:17:44 +00:00
Owen Anderson
3dd6c949a5 Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
llvm-svn: 143208
2011-10-28 18:02:13 +00:00
Dan Gohman
dedcc22bcd Reapply r143177 and r143179 (reverting r143188), with scheduler
fixes: Use a separate register, instead of SP, as the
calling-convention resource, to avoid spurious conflicts with
actual uses of SP. Also, fix unscheduling of calling sequences,
which can be triggered by pseudo-two-address dependencies.

llvm-svn: 143206
2011-10-28 17:55:38 +00:00
Owen Anderson
5ccc0979a0 Revert r143202.
llvm-svn: 143203
2011-10-28 17:38:30 +00:00
Owen Anderson
5c58be2852 Specify fixed bits on CPS instructions to enable roundtripping.
llvm-svn: 143202
2011-10-28 17:29:39 +00:00
Jim Grosbach
72ab459378 Thumb2 ADD/SUB instructions encoding selection outside IT block.
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).

rdar://10348481

llvm-svn: 143201
2011-10-28 16:57:07 +00:00
Jim Grosbach
188121af2e Allow register classes to match a containing class in InstAliases.
If the register class in the source alias is a subclass of the register class
of the actual instruction, the alias can still match OK since the constraints
are strictly a subset of what the instruction can actually handle.

llvm-svn: 143200
2011-10-28 16:43:40 +00:00
NAKAMURA Takumi
2ea569c7e0 test/MC/AsmParser/2011-09-06-NoNewline.s: Add explicit -mtriple=i386. It uses X86 instruction.
FIXME: Would it be reproduced without target-specific operands?
FIXME: Why run llvm-mc as the same input by 3 times?
llvm-svn: 143195
2011-10-28 14:12:30 +00:00
NAKAMURA Takumi
bcfac720a7 Dwarf: [PR11022] Fix emitting DW_AT_const_value(>i64), to be host-endian-neutral.
Don't assume APInt::getRawData() would hold target-aware endianness nor host-compliant endianness. rawdata[0] holds most lower i64, even on big endian host.

FIXME: Add a testcase for big endian target.

FIXME: Ditto on CompileUnit::addConstantFPValue() ?
llvm-svn: 143194
2011-10-28 14:12:22 +00:00
Stepan Dyatkovskiy
d1216f47ca uint64 formatted output: replaced %llx with PRIx64 macro.
llvm-svn: 143191
2011-10-28 13:07:32 +00:00
Benjamin Kramer
66c9d07549 Use BranchProbability compare operators.
llvm-svn: 143190
2011-10-28 11:14:31 +00:00
NAKAMURA Takumi
b5df9f3cc1 test/CodeGen/X86/2010-08-10-DbgConstant.ll: Add explicit -mtriple=i686-linux. It must be for elf!
llvm-svn: 143189
2011-10-28 10:50:52 +00:00
Duncan Sands
a6507c4bcb Speculatively disable Dan's commits 143177 and 143179 to see if
it fixes the dragonegg self-host (it looks like gcc is miscompiled).
Original commit messages:
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.

Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.

Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.

Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.

This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.

Delete #if 0 code accidentally left in.

llvm-svn: 143188
2011-10-28 09:55:57 +00:00
Nick Lewycky
5758d6af22 Always use the string pool, even when it makes the .o larger. This may help
tools that read the debug info in the .o files by making the DIE sizes more
consistent.

llvm-svn: 143186
2011-10-28 05:29:47 +00:00
Andrew Trick
77532be5e0 LFTR should avoid a type mismatch with null pointer IVs.
Fixes rdar://10359193 Indvar LinearFunctionTestReplace assertion

llvm-svn: 143183
2011-10-28 03:45:11 +00:00
Dan Gohman
fb95b6bd5e Delete #if 0 code accidentally left in.
llvm-svn: 143179
2011-10-28 01:41:21 +00:00
Dan Gohman
484df993bd Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.

Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.

Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.

Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.

This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.

llvm-svn: 143177
2011-10-28 01:29:32 +00:00
Peter Collingbourne
91824cb6ac Have llvm-config --cppflags print correct flags when in CMake build directory
Previously, if invoked from a CMake build directory, 'llvm-config
--cppflags' and friends would only print a -I flag for the build
directory's header search path, because it would assume that it was
already installed, not recognising its parent directory as being the
build directory.  Teach llvm-config about CMake build directories
so that it prints a -I for both the source and build directory's
search paths.

llvm-svn: 143171
2011-10-28 01:02:16 +00:00
Jim Grosbach
dac7815a91 ARM Allow 'q' registers in VLD/VST vector lists.
Just treat it as if the constituent D registers where specified.

rdar://10348896

llvm-svn: 143167
2011-10-28 00:06:50 +00:00
Dan Gohman
892b86e74c Remove the Alpha backend.
llvm-svn: 143164
2011-10-27 22:56:32 +00:00
Owen Anderson
f22cd77ceb Add testcase for r143162.
llvm-svn: 143163
2011-10-27 22:54:14 +00:00