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aa96c057be
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16522 Commits

Author SHA1 Message Date
Jim Grosbach
aa96c057be Pseudo-ize ARM MOVPCRX 
llvm-svn: 120442
 2010-11-30 18:56:36 +00:00
Owen Anderson
6581027075 Provide encodings for a few more load/store variants. 
llvm-svn: 120439
 2010-11-30 18:38:28 +00:00
Jim Grosbach
cb8193b99e Pseudo-ize BX_CALL and friends. Remove dead instruction format classes. 
rdar://8685712

llvm-svn: 120438
 2010-11-30 18:30:19 +00:00
Che-Liang Chiou
f594fe5fc5 ptx: add command-line options for gpu target and ptx version 
llvm-svn: 120423
 2010-11-30 10:14:14 +00:00
Eric Christopher
1a99e7ebdb Fix some grammar in comments I noticed. 
llvm-svn: 120416
 2010-11-30 09:11:54 +00:00
Eric Christopher
d8e045d29e This defaults to GenericDomain. 
llvm-svn: 120415
 2010-11-30 09:11:07 +00:00
Eric Christopher
6a21ceab5c Implement a PseudoI class and transfer the sse instructions over to use 
it.

llvm-svn: 120412
 2010-11-30 08:57:23 +00:00
Eric Christopher
73365ae8b6 Fix insertion point in pcmp expander. 
While I'm there, clean up too many \n even for me.

llvm-svn: 120411
 2010-11-30 08:20:21 +00:00
Eric Christopher
2170738538 Fix some cleanups from my last patch. 
llvm-svn: 120410
 2010-11-30 08:10:28 +00:00
Bill Wendling
ae920bcc50 Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost 
certainly be made more generic. But it does allow us to parse something like:

          ldr     r3, [r2, r4]

correctly in Thumb mode.

llvm-svn: 120408
 2010-11-30 07:44:32 +00:00
Che-Liang Chiou
df20cec4fb ptx: add ld instruction 
support register and register-immediate addressing mode

todo: immediate and register-register addressing mode
llvm-svn: 120407
 2010-11-30 07:34:44 +00:00
Eric Christopher
f27f0b5234 Rewrite mwait and monitor support and custom lower arguments. 
Fixes PR8573.

llvm-svn: 120404
 2010-11-30 07:20:12 +00:00
Bill Wendling
a3cc011fc5 Minor cleanups. No functional change. 
llvm-svn: 120372
 2010-11-30 00:50:22 +00:00
Bill Wendling
5030f8359b s/ARM::BRIND/ARM::BX/g to coincide with r120366. 
llvm-svn: 120371
 2010-11-30 00:48:15 +00:00
Bill Wendling
6bcbf9bd7c Add correct encoding for "bl __aeabi_read_tp". However, the asm matcher isn't 
able to match this yet.

llvm-svn: 120369
 2010-11-30 00:34:08 +00:00
Jim Grosbach
6c0221e3ae Rename BX/BRIND/etc patterns to clarify which is actually the BX instruction 
and which are pseudos.

llvm-svn: 120366
 2010-11-30 00:24:05 +00:00
Bill Wendling
7cbe5a236c Add some encoding for the adr instruction. Labels still need to be finished. 
llvm-svn: 120365
 2010-11-30 00:18:30 +00:00
Owen Anderson
b6e1c56c79 Correct Thumb2 encodings for a much wider range of loads and stores. 
llvm-svn: 120364
 2010-11-30 00:14:31 +00:00
Jim Grosbach
5f2a3880a8 Make a few more ARM pseudo instructions actually use the PseudoInst base class. 
llvm-svn: 120362
 2010-11-30 00:09:06 +00:00
Bill Wendling
9859e95ca2 Predicate encoding should be withing {}s. And general cleanup. 
llvm-svn: 120361
 2010-11-30 00:08:20 +00:00
Bill Wendling
6b680b11e8 Predicate encoding should be withing {}s. 
llvm-svn: 120360
 2010-11-30 00:05:25 +00:00
Bob Wilson
f5eece615c Fix the encoding of VLD4-dup alignment. 
The only reasonable way I could find to do this is to provide an alternate
version of the addrmode6 operand with a different encoding function.  Use it
for all the VLD-dup instructions for the sake of consistency.

llvm-svn: 120358
 2010-11-30 00:00:42 +00:00
Bob Wilson
1be989686c Rename VLDnDUP instructions with double-spaced registers 
in an attempt to make things a little more consistent.

llvm-svn: 120357
 2010-11-30 00:00:38 +00:00
Bob Wilson
bd3d3d2937 Add support for NEON VLD3-dup instructions. 
The encoding for alignment in VLD4-dup instructions is still a work in progress.

llvm-svn: 120356
 2010-11-30 00:00:35 +00:00
Jim Grosbach
58e4c01d0d Simplify definitions of the ARM eh.sjlj.*jmp pseudo instructions. 
llvm-svn: 120354
 2010-11-29 23:51:31 +00:00
Jim Grosbach
b796df67e9 Parameterize ARMPseudoInst size property. 
llvm-svn: 120353
 2010-11-29 23:48:41 +00:00
Jim Grosbach
81880e96fc Add a few missing initializers. 
llvm-svn: 120350
 2010-11-29 23:41:10 +00:00
Jim Grosbach
4e37703b2c Nuke trailing whitespace. 
llvm-svn: 120344
 2010-11-29 23:18:01 +00:00
Jim Grosbach
d92d1fa9e6 Nuke a FIXME. No need to be fancier here, as ARM handles constant pools 
locations and formatting specially. rdar://7353441

llvm-svn: 120343
 2010-11-29 23:09:20 +00:00
Owen Anderson
14abbb1a2e Provide Thumb2 encodings for basic loads and stores. 
llvm-svn: 120340
 2010-11-29 22:44:32 +00:00
Evan Cheng
78baa6f30d Mark Darwin call instructions as using "r7" to prevent the frame-register 
assignment instructions from being moved below / above calls.
rdar://8690640

llvm-svn: 120339
 2010-11-29 22:43:27 +00:00
Jim Grosbach
90cb1bbd23 Nuke dead isCodeGenOnly annotation and extraneous comment. 
llvm-svn: 120338
 2010-11-29 22:40:58 +00:00
Jim Grosbach
208782384a tidy up. 
llvm-svn: 120335
 2010-11-29 22:38:48 +00:00
Bill Wendling
c2693dcc02 Thumb encodings for conditional moves. 
llvm-svn: 120334
 2010-11-29 22:37:46 +00:00
Jim Grosbach
89e90b7310 Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw 
instructions. This simplifies instruction printing and disassembly.

llvm-svn: 120333
 2010-11-29 22:37:40 +00:00
Bill Wendling
15e68b7a35 Refactor some of the "disassembly-only" instructions into a base class. This 
reduces some code duplication.

llvm-svn: 120326
 2010-11-29 22:15:03 +00:00
Eric Christopher
625238ff3e Update fastisel for the changes in r120272. 
llvm-svn: 120324
 2010-11-29 21:56:23 +00:00
Jim Grosbach
71042b51a1 Rename t2 TBB and TBH instructions to reference that they encode the jump table 
data. Next up, pseudo-izing them.

llvm-svn: 120320
 2010-11-29 21:28:32 +00:00
Owen Anderson
4b82810d8c Improving the factoring of several instruction encodings. 
llvm-svn: 120317
 2010-11-29 20:38:48 +00:00
Bob Wilson
aa197b07e6 Add support for NEON VLD3-dup instructions. 
llvm-svn: 120312
 2010-11-29 19:35:29 +00:00
Bob Wilson
cb675664c4 Fix copy-and-paste errors in VLD2-dup scheduling itineraries. 
llvm-svn: 120311
 2010-11-29 19:35:23 +00:00
Jim Grosbach
3e84f9d6cb ARM Pseudo-ize tBR_JTr. 
llvm-svn: 120310
 2010-11-29 19:32:47 +00:00
Owen Anderson
049177ff7f Thumb2 encodings for MSR and MRS. 
llvm-svn: 120309
 2010-11-29 19:29:15 +00:00
Owen Anderson
78d84a1921 Thumb2 encodings for system instructions. 
llvm-svn: 120307
 2010-11-29 19:22:08 +00:00
Owen Anderson
b29182b60f Thumb2 encodings for branches and IT blocks. 
llvm-svn: 120306
 2010-11-29 18:54:38 +00:00
Jim Grosbach
0d235c0c37 The ARM BR_JT* pseudos don't need to use the printer jtblock_operand node to 
get the pretty-printer. That's handled explicityly by the MC lowering now.

llvm-svn: 120305
 2010-11-29 18:53:24 +00:00
Michael J. Spencer
4a63404543 I swear I did a make clean and make before committing all this... 
llvm-svn: 120304
 2010-11-29 18:47:54 +00:00
Jim Grosbach
9e2ed21ad0 Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos. 
llvm-svn: 120303
 2010-11-29 18:37:44 +00:00
Michael J. Spencer
d5ec932c3a Merge System into Support. 
llvm-svn: 120298
 2010-11-29 18:16:10 +00:00
Kalle Raiskila
71dec6ff42 Handle lshr for i128 correctly on SPU also when 
shiftamount > 7.

llvm-svn: 120288
 2010-11-29 14:44:28 +00:00