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Commit Graph

276 Commits

Author SHA1 Message Date
Chad Rosier
aaa3bb367a [AArch64] Add support for NEON scalar absolute value instruction.
llvm-svn: 192842
2013-10-16 21:04:34 +00:00
Chad Rosier
929e07c8ea Update comment.
llvm-svn: 192806
2013-10-16 16:30:10 +00:00
Chad Rosier
a195d145b8 [AArch64] Add support for NEON scalar signed saturating accumulated of unsigned
value and unsigned saturating accumulate of signed value instructions.

llvm-svn: 192800
2013-10-16 16:09:02 +00:00
Will Dietz
53ec6883be TypeFinder: prefer iterative algorithm to keep stack usage low.
Introduce subtype_reverse_iterator to maintain
the numbering assigned during the recursive type walk.

llvm-svn: 192770
2013-10-16 04:10:06 +00:00
Craig Topper
037594e792 Remove x86_sse42_crc32_64_8 intrinsic. It has no functional difference from x86_sse42_crc32_32_8 and was not mapped to a clang builtin. I'm not even sure why this form of the instruction is even called out explicitly in the docs. Also add AutoUpgrade support to convert it into the other intrinsic with appropriate trunc and zext.
llvm-svn: 192672
2013-10-15 05:20:47 +00:00
Chad Rosier
40761dc629 [AArch64] Add support for NEON scalar integer compare instructions.
llvm-svn: 192596
2013-10-14 14:37:20 +00:00
Rafael Espindola
f0991565b5 Add a GlobalAlias::isValidLinkage to reduce code duplication.
Thanks to Reid Kleckner for the suggestion.

llvm-svn: 192298
2013-10-09 16:07:32 +00:00
Elena Demikhovsky
f24ecf7862 AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics.
llvm-svn: 192283
2013-10-09 08:16:14 +00:00
Chad Rosier
d30c4af71b [AArch64] Add support for NEON scalar floating-point reciprocal estimate,
reciprocal exponent, and reciprocal square root estimate instructions.

llvm-svn: 192242
2013-10-08 22:09:04 +00:00
Matt Arsenault
f3a608f7ff Fix duplicated assertions.
Do what some other instructions do, and add an assert method.

llvm-svn: 192236
2013-10-08 21:11:12 +00:00
Chad Rosier
e281a17b84 [AArch64] Add support for NEON scalar signed/unsigned integer to floating-point
convert instructions.

llvm-svn: 192231
2013-10-08 20:43:30 +00:00
Benjamin Kramer
f9db6465f7 IRBuilder: Downgrade InsertPointGuard's instruction pointer to a raw pointer.
Sadly this loses the checking from AssertingVH, but apparently storing the
end() of a BasicBlock into an AssertingVH has bad consequences as it's not
really an instruction.

llvm-svn: 192209
2013-10-08 17:44:56 +00:00
Matt Arsenault
9c8541d286 Change objectsize intrinsic to accept different address spaces.
Bitcasting everything to i8* won't work. Autoupgrade the old
intrinsic declarations to use the new mangling.

llvm-svn: 192117
2013-10-07 18:06:48 +00:00
Elena Demikhovsky
cb8eaca2e4 AVX-512: added scalar convert instructions and intrinsics.
Fixed load folding in VPERM2I instruction.

llvm-svn: 192063
2013-10-06 13:11:09 +00:00
Craig Topper
0a8f3fc996 Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns are sufficient.
llvm-svn: 192039
2013-10-05 19:22:59 +00:00
Jiangning Liu
6d9b4a0e25 Implement aarch64 neon instruction set AdvSIMD (Across).
llvm-svn: 192028
2013-10-05 08:22:10 +00:00
Craig Topper
5ac188d0f2 Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao.
llvm-svn: 191871
2013-10-03 04:16:45 +00:00
Pete Cooper
9b04f39eb6 Add v4f16 to supported value types.
This is useful for some ARM intrinsics such as VCVTN which does a <4 x float> <-> <4 x half> conversion.

llvm-svn: 191870
2013-10-03 03:29:21 +00:00
Joey Gouly
12afb60cf2 [ARM] Introduce the 'sevl' instruction in ARMv8.
This also removes the restriction on the immediate field of the 'hint'
instruction.

llvm-svn: 191744
2013-10-01 12:39:11 +00:00
Benjamin Kramer
33abdcddb3 IRBuilder: Add RAII objects to reset insertion points or fast math flags.
Inspired by the object from the SLPVectorizer. This found a minor bug in the
debug loc restoration in the vectorizer where the location of a following
instruction was attached instead of the location from the original instruction.

llvm-svn: 191673
2013-09-30 15:39:48 +00:00
Benjamin Kramer
bd7dc07ee2 IRBuilder: Move fast math flags to IRBuilderBase.
They don't depend on the templated stuff.

llvm-svn: 191672
2013-09-30 15:39:27 +00:00
Yunzhong Gao
e51da27a74 Adding intrinsics to the llvm backend for TBM instruction set.
Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750

llvm-svn: 191539
2013-09-27 18:38:42 +00:00
Daniel Sanders
0987676281 [mips][msa] Implemented insert.d intrinsic.
This intrinsic is lowered into an equivalent INSERT_VECTOR_ELT which is
further lowered into a sequence of insert.w's on MIPS32.

llvm-svn: 191521
2013-09-27 13:36:54 +00:00
Daniel Sanders
3c43957555 [mips][msa] Implemented fill.d intrinsic.
This intrinsic is lowered into an equivalent BUILD_VECTOR which is further
lowered into a sequence of insert.w's on MIPS32.

llvm-svn: 191519
2013-09-27 13:20:41 +00:00
Daniel Sanders
935673af60 [mips][msa] Implemented copy_[us].d intrinsic.
This intrinsic is lowered into equivalent copy_s.w instructions during
legalization.

llvm-svn: 191518
2013-09-27 13:04:21 +00:00
Daniel Sanders
7c64721346 [mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics)
llvm-svn: 191301
2013-09-24 14:02:15 +00:00
Daniel Sanders
0167ec55f4 [mips][msa] Added support for matching bsel and bseli from normal IR (i.e. not intrinsics)
This required correcting the definition of the bsel and bseli intrinsics.

llvm-svn: 191290
2013-09-24 12:04:44 +00:00
Jiangning Liu
5867567c41 Initial support for Neon scalar instructions.
Patch by Ana Pazos.

1.Added support for v1ix and v1fx types.
2.Added Scalar Pairwise Reduce instructions.
3.Added initial implementation of Scalar Arithmetic instructions.

llvm-svn: 191263
2013-09-24 02:47:27 +00:00
Reid Kleckner
333fd129ac Explicitly request unsigned enum types when desired
The underlying type of all plain enums in MSVC is 'int', even if the
enumerator contains large 32-bit unsigned values or values greater than
UINT_MAX.  The only way to get a large or unsigned enum type is to
request it explicitly with the C++11 strong enum types feature.

However, since LLVM isn't C++11 yet, I had to add a conditional
LLVM_ENUM_INT_TYPE to Compiler.h to control its usage.

The motivating true positive for this change is compiling PointerIntPair
with MSVC for win64.  The PointerIntMask value is supposed to be pointer
sized value of all ones with some low zeros.  Instead, it's truncated to
32-bits!  We are only saved later because it is sign extended back in
the AND with int64_t, and we happen to want all ones.

This silences lots of -Wmicrosoft warnings during a clang self-host
targeting Windows.

llvm-svn: 191241
2013-09-23 23:26:57 +00:00
Daniel Sanders
34cb8f3e4d [mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics)
Changes to MIPS SelectionDAG:
* Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single
  operation and implemented the DAG combines necessary to fold sign/zero
  extends into the extract.

llvm-svn: 191199
2013-09-23 14:03:12 +00:00
Amara Emerson
7ad0409c56 [ARMv8] Add support for the v8 cryptography extensions.
llvm-svn: 190996
2013-09-19 11:59:01 +00:00
Joey Gouly
e14ac63b96 [ARMv8] Add CRC instructions.
Patch by Bradley Smith!

llvm-svn: 190928
2013-09-18 09:45:55 +00:00
Ben Langmuir
c0ab36fe2e Add llvm.x86.* intrinsics for Intel SHA Extensions
Add llvm.x86.* intrinsics for all of the Intel SHA Extensions instructions, as
well as tests. Also remove mayLoad and hasSideEffects, which can be inferred
from the instruction patterns.

llvm-svn: 190864
2013-09-17 13:44:39 +00:00
Craig Topper
3a6a903891 Make a more clear AVX-512 section header that matches similar in the file.
llvm-svn: 190843
2013-09-17 03:34:09 +00:00
Matt Arsenault
513e7539be MemCpyOptimizer: Use max legal int size instead of pointer size
If there are no legal integers, assume 1 byte.

This makes more sense than using the pointer size as
a guess for the maximum GPR width.

It is conceivable to want to use some 64-bit pointers
on a target where 64-bit integers aren't legal.

llvm-svn: 190817
2013-09-16 22:43:16 +00:00
Peter Collingbourne
cf3b1a2910 Implement function prefix data as an IR feature.
Previous discussion:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-July/063909.html

Differential Revision: http://llvm-reviews.chandlerc.com/D1191

llvm-svn: 190773
2013-09-16 01:08:15 +00:00
Matt Arsenault
279eb73c79 Fix comment to match what the assert actually enforces
llvm-svn: 190566
2013-09-12 01:07:54 +00:00
Daniel Sanders
534d28aa11 [mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsics
The elements of the operands should be half the width of the elements of
the result.

llvm-svn: 190505
2013-09-11 09:59:17 +00:00
Daniel Sanders
32227b7995 [mips][msa] Removed unsupported dot product instructions (dotp_[su].b)
The dotp_[su].b instructions never existed in any revision of the MSA spec.

llvm-svn: 190398
2013-09-10 09:51:43 +00:00
Bob Wilson
6c7d3717b3 Revert patches to add case-range support for PR1255.
The work on this project was left in an unfinished and inconsistent state.
Hopefully someone will eventually get a chance to implement this feature, but
in the meantime, it is better to put things back the way the were.  I have
left support in the bitcode reader to handle the case-range bitcode format,
so that we do not lose bitcode compatibility with the llvm 3.3 release.

This reverts the following commits: 155464, 156374, 156377, 156613, 156704,
156757, 156804 156808, 156985, 157046, 157112, 157183, 157315, 157384, 157575,
157576, 157586, 157612, 157810, 157814, 157815, 157880, 157881, 157882, 157884,
157887, 157901, 158979, 157987, 157989, 158986, 158997, 159076, 159101, 159100,
159200, 159201, 159207, 159527, 159532, 159540, 159583, 159618, 159658, 159659,
159660, 159661, 159703, 159704, 160076, 167356, 172025, 186736

llvm-svn: 190328
2013-09-09 19:14:35 +00:00
Manman Ren
de03bcdbec TBAA: add isTBAAVtableAccess to MDNode so clients can call the function
instead of having its own implementation.

The implementation of isTBAAVtableAccess is in TypeBasedAliasAnalysis.cpp
since it is related to the format of TBAA metadata.

The path for struct-path tbaa will be exercised by
test/Instrumentation/ThreadSanitizer/read_from_global.ll, vptr_read.ll, and
vptr_update.ll when struct-path tbaa is on by default.

llvm-svn: 190216
2013-09-06 22:47:05 +00:00
Matt Arsenault
4c2083b14a Use type helper functions.
llvm-svn: 190113
2013-09-06 00:37:24 +00:00
Joey Gouly
071ca2ff6d [ARMv8] Implement the new DMB/DSB operands.
This removes the custom ISD Node: MEMBARRIER and replaces it
with an intrinsic.

llvm-svn: 190055
2013-09-05 15:35:24 +00:00
Rafael Espindola
357980289a Revert "Add r159136 back now that pr13124 has been fixed."
This reverts commit r189886.

I found a corner case where this optimization is not valid:

Say we have a "linkonce_odr unnamed_addr" in two translation units:
* In TU 1 this optimization kicks in and makes it hidden.
* In TU 2 it gets const merged with a constant that is *not* unnamed_addr,
  resulting in a non unnamed_addr constant with default visibility.
* The static linker rules for combining visibility them produce a hidden
  symbol, which is incorrect from the point of view of the non unnamed_addr
  constant.

The one place we can do this is when we know that the symbol is not used from
another TU in the same shared object, i.e., during LTO. I will move it there.

llvm-svn: 189954
2013-09-04 16:09:01 +00:00
Hao Liu
b344ca7aa3 Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:
sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll
 and 4 convert instructions:
      scvtf,ucvtf,fcvtzs,fcvtzu

llvm-svn: 189925
2013-09-04 09:28:24 +00:00
Rafael Espindola
8b9c0a576e Add r159136 back now that pr13124 has been fixed.
Original message:
If a constant or a function has linkonce_odr linkage and unnamed_addr, mark
hidden. Being linkonce_odr guarantees that it is available in every dso that
needs it. Being a constant/function with unnamed_addr guarantees that the
copies don't have to be merged.

llvm-svn: 189886
2013-09-03 23:34:36 +00:00
Daniel Sanders
3fe5e48ec9 [mips][msa] Added IntrNoMem and removed Commutative from sub intrinsics.
This changes the SelectionDAG nodes from ISD::INTRINSIC_W_CHAIN to
ISD::INTRINSIC_WO_CHAIN which enables easy lowering to equivalent SelectionDAG
nodes (e.g. __builtin_msa_sub_w -> ISD::SUB) in future patches since nodes
such as ISD::SUB do not have a chain.
It also corrects an obvious mistake, namely that the subtract intrinsics were
marked as being commutative.

As per a similar change in r189106
(http://llvm.org/viewvc/llvm-project?rev=189106&view=rev) there isn’t a new
testcase in this patch since the existing tests should test the intrinsics to
the same standard and the best I can do for a testcase would be a fragile
pass/maybe test of whether memory operations can (and do) cross the intrinsic.

llvm-svn: 189784
2013-09-03 09:45:20 +00:00
Daniel Sanders
96e29ee174 [mips][msa] Added IntrNoMem to the floating-point intrinsics.
This changes the SelectionDAG nodes from ISD::INTRINSIC_W_CHAIN to
ISD::INTRINSIC_WO_CHAIN which enables easy lowering to equivalent SelectionDAG
nodes (e.g. __builtin_msa_fadd_w -> ISD::FADD) in future patches since nodes
such as ISD::FADD do not have a chain.

As per a similar change in r189106
(http://llvm.org/viewvc/llvm-project?rev=189106&view=rev) there isn’t a new
testcase in this patch since the existing tests should test the intrinsics to
the same standard and the best I can do for a testcase would be a fragile
pass/maybe test of whether memory operations can (and do) cross the intrinsic.

llvm-svn: 189782
2013-09-03 09:35:20 +00:00
Tim Northover
490c4c1bda ARM: remove unused v(add|sub)hn and vqdml[as]l intrinsics.
Clang is now generating cleaner IR, so this removes the old variants which
should be completely unused.

llvm-svn: 189481
2013-08-28 14:33:33 +00:00
Daniel Sanders
7d6b0c31fc [mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v
These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes,
are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as
a branch/mov sequence to evaluate to 0 or 1.

Note: The resulting code is sub-optimal since it doesnt seem to be possible
to feed the result of an intrinsic directly into a brcond. At the moment
it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily
evaluates the boolean twice.

llvm-svn: 189478
2013-08-28 12:14:50 +00:00