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Author SHA1 Message Date
Chris Lattner
7b7ea7c7bd Tighten up some checks 
llvm-svn: 24817
 2005-12-18 06:40:34 +00:00
Jim Laskey
831eca00db Fix a bug Sabre was having where the DAG root was a group. The group dominator 
needed to be added to the ordering list, not the first member of the group.

llvm-svn: 24816
 2005-12-18 04:40:52 +00:00
Jim Laskey
a06085f024 Groups were not emitted if the dominator node and the node in the ordering list 
were not the same node.  Ultimately the test was bogus.

llvm-svn: 24815
 2005-12-18 03:59:21 +00:00
Nate Begeman
c14ad3dec7 Since extload can also be used by FP, split STDIntExtLoad into two parts, 
one for use with extload, one for use with sextload and zextload, which
are integer only.

llvm-svn: 24814
 2005-12-18 02:48:48 +00:00
Chris Lattner
2aab8f4471 Add constant pool support, including folding into addresses. 
Pretty print addresses a bit, to not print [%r1+%g0]: just print [%r1]

llvm-svn: 24813
 2005-12-18 02:37:35 +00:00
Chris Lattner
cba8a96bd0 Teach the addressing mode stuff to fold "%lo" into 'ri' addressing modes, 
allowing us to compile this:

to this:

%G1 = external global int
%G2 = external global int
void %test() {
        %X = load int* %G1
        store int %X, int* %G2
        ret void
}

test:
        save -96, %sp, %sp
        sethi %hi(G1), %l0
        ld [%l0+%lo(G1)], %l0
        sethi %hi(G2), %l1
        st %l0, [%l1+%lo(G2)]
        restore %g0, %g0, %g0
        retl
        nop

instead of this:

test:
        save -96, %sp, %sp
        sethi %hi(G1), %l0
        or %g0, %lo(G1), %l1
        ld [%l1+%l0], %l0
        sethi %hi(G2), %l1
        or %g0, %lo(G2), %l2
        st %l0, [%l2+%l1]
        restore %g0, %g0, %g0
        retl
        nop

llvm-svn: 24812
 2005-12-18 02:27:00 +00:00
Chris Lattner
5303e59b7a Add initial support for global variables, and fix a bug in addr mode selection 
where we didn't select the operands.

llvm-svn: 24811
 2005-12-18 02:10:39 +00:00
Chris Lattner
1294e27969 Claiming that branch targets are registers is not very wholesome. Change them 
to be basic blocks.  Also, add uncond branches.

llvm-svn: 24810
 2005-12-18 01:46:58 +00:00
Chris Lattner
f3a888d1dd Add unordered comparisons 
llvm-svn: 24809
 2005-12-18 01:41:39 +00:00
Chris Lattner
66e29f7ead Add patterns to the rest of the int condbranches and some of the fp branches 
llvm-svn: 24808
 2005-12-18 01:38:19 +00:00
Chris Lattner
47785d8fc3 Add initial conditional branch support. This doesn't actually work yet due 
to a bug in the scheduler.

llvm-svn: 24807
 2005-12-18 01:20:35 +00:00
Chris Lattner
bb6af65f76 Simplify code 
llvm-svn: 24806
 2005-12-18 01:03:46 +00:00
Chris Lattner
9f0ac41d5c Eliminate CMPri, which is a synonym for SUBCCri 
llvm-svn: 24805
 2005-12-17 23:52:08 +00:00
Chris Lattner
bdb696294e allow custom expansion of BR_CC 
llvm-svn: 24804
 2005-12-17 23:46:46 +00:00
Chris Lattner
95e9327303 add fneg,fabs,fsqrt instructions 
llvm-svn: 24803
 2005-12-17 23:20:27 +00:00
Chris Lattner
a9adf79113 Add patterns for fround/fextend and the funny fsmuld instruction 
llvm-svn: 24802
 2005-12-17 23:14:30 +00:00
Chris Lattner
ac03e1e55e Add FP +,-,*,/ 
llvm-svn: 24801
 2005-12-17 23:10:46 +00:00
Chris Lattner
13253a829a Give patterns to F3_3 instructions 
llvm-svn: 24800
 2005-12-17 23:05:35 +00:00
Chris Lattner
057fbaea0d Implement 64-bit add/sub, make sure to receive and return 64-bit args with 
the right halves in the right regs

llvm-svn: 24799
 2005-12-17 22:55:57 +00:00
Chris Lattner
a4865938dc implement div and rem 
llvm-svn: 24798
 2005-12-17 22:39:19 +00:00
Chris Lattner
88a3754b46 implement MULHU/MULHS for 64-bit multiplies 
llvm-svn: 24797
 2005-12-17 22:30:00 +00:00
Chris Lattner
7f9e66063d Add patterns for multiply, simplify Y register handling stuff, add RDY instruction 
llvm-svn: 24796
 2005-12-17 22:22:53 +00:00
Chris Lattner
a4dbacd0d6 Make the addressing modes smarter 
llvm-svn: 24795
 2005-12-17 21:25:27 +00:00
Chris Lattner
9bd197adae remove some unused instructions 
llvm-svn: 24794
 2005-12-17 21:13:50 +00:00
Chris Lattner
a17cbf352e add andn/orn/xorn patterns. This allows us to compile this: 
long %test(ubyte, short, long %X, long %Y) {
  %A = xor long %X, -1
  %B = and long %Y, %A
  ret long %B
}

to this:

test:
        save -96, %sp, %sp
        andn %i4, %i2, %i0
        andn %i5, %i3, %i1
        restore %g0, %g0, %g0
        retl
        nop

instead of this:

test:
        save -96, %sp, %sp
        xor %i2, -1, %l0
        xor %i3, -1, %l1
        and %i4, %l0, %i0
        and %i5, %l1, %i1
        restore %g0, %g0, %g0
        retl
        nop

The simpleisel emits:  :(

test:
        save -96, %sp, %sp
        or %g0, -1, %l0
        or %g0, -1, %l0
        or %g0, -1, %l0
        or %g0, -1, %l1
        xor %i2, %l0, %l0
        xor %i3, %l1, %l1
        and %i4, %l0, %i0
        and %i5, %l1, %i1
        restore %g0, %g0, %g0
        retl
        nop

llvm-svn: 24793
 2005-12-17 21:05:49 +00:00
Chris Lattner
3afda7194f Add support for 64-bit arguments 
llvm-svn: 24792
 2005-12-17 20:59:06 +00:00
Chris Lattner
c1ab8a5e42 Sparc doesn't have sext_inreg 
llvm-svn: 24791
 2005-12-17 20:50:42 +00:00
Chris Lattner
a57b8986ea add patterns for FP stores 
llvm-svn: 24790
 2005-12-17 20:47:16 +00:00
Chris Lattner
abb86e4e22 Add [reg+reg] integer stores 
llvm-svn: 24789
 2005-12-17 20:44:36 +00:00
Chris Lattner
f9bc70e0ef Add store patterns 
llvm-svn: 24788
 2005-12-17 20:42:55 +00:00
Chris Lattner
171e828d2d add truncstore 
llvm-svn: 24787
 2005-12-17 20:42:29 +00:00
Chris Lattner
bdfee98ec0 add fp load patterns, switch rest of loads and stores to use addrmodes 
llvm-svn: 24786
 2005-12-17 20:32:47 +00:00
Chris Lattner
d775f1de68 Add integer load[r+r] forms. 
llvm-svn: 24785
 2005-12-17 20:26:45 +00:00
Chris Lattner
d09afb735d Rename load/store instructions to include an RI suffix 
llvm-svn: 24784
 2005-12-17 20:18:49 +00:00
Chris Lattner
9133c2c38b Add patterns for the rest of the loads. Add 'ri' suffixes to the load and store insts 
llvm-svn: 24783
 2005-12-17 20:18:24 +00:00
Chris Lattner
3e51b620ec Add basic addressing mode support and one load. 
llvm-svn: 24782
 2005-12-17 20:04:49 +00:00
Chris Lattner
399dfec939 eliminate some redundancy 
llvm-svn: 24781
 2005-12-17 19:47:05 +00:00
Chris Lattner
e441738cef Use a combination of sethi and or to build arbitrary immediates. 
llvm-svn: 24780
 2005-12-17 19:41:43 +00:00
Chris Lattner
39740d3207 Use sethi to build large immediates with zeros at the bottom 
llvm-svn: 24779
 2005-12-17 19:37:00 +00:00
Chris Lattner
5893b95caa Add shift and small immediate support 
llvm-svn: 24778
 2005-12-17 19:07:57 +00:00
Chris Lattner
81b13ccb01 Add some basic reg-reg instructions 
llvm-svn: 24777
 2005-12-17 18:53:33 +00:00
Chris Lattner
058fe7d1ed Add empty patterns to all F3_1 instructions 
llvm-svn: 24776
 2005-12-17 18:49:14 +00:00
Evan Cheng
56649f9616 Darwin API issue: indirect load of external and weak symbols. 
llvm-svn: 24775
 2005-12-17 09:13:43 +00:00
Chris Lattner
2ba4a8584c Add some simple integer patterns. This allows us to compile this: 
int %test(int %A) {
  %B = add int %A, 1
  %C = xor int %B, 123
  ret int %C
}

into this:

test:
        save -96, %sp, %sp
        add %i0, 1, %l0
        xor %l0, 123, %i0
        restore %g0, %g0, %g0
        retl
        nop

for example.  I guess it would make sense to add reg/reg versions too.

llvm-svn: 24774
 2005-12-17 08:26:38 +00:00
Chris Lattner
4de7491c52 Implement ret with operand, giving us this: 
int %test(int %A) {
  ret int %A
}

llvm-svn: 24773
 2005-12-17 08:15:09 +00:00
Chris Lattner
b877ae7929 Add a pattern for 'ret'. This now compiles: 
void %test() { ret void }

:)

llvm-svn: 24772
 2005-12-17 08:08:42 +00:00
Chris Lattner
e7408707fd Add empty patterns for F3_2 instructions 
llvm-svn: 24771
 2005-12-17 08:06:43 +00:00
Chris Lattner
3fca9488d2 Implement LowerArguments, at least for the first 6 integer args 
llvm-svn: 24770
 2005-12-17 08:03:24 +00:00
Chris Lattner
62aadddb9d Add the framework for a dag-dag isel 
llvm-svn: 24769
 2005-12-17 07:47:01 +00:00
Evan Cheng
a3ff796fda Remove a few lines of dead code. 
llvm-svn: 24768
 2005-12-17 07:18:44 +00:00