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Commit Graph

77831 Commits

Author SHA1 Message Date
Eric Christopher
64306dbfc6 Fix comment formatting.
llvm-svn: 232076
2015-03-12 18:23:01 +00:00
Eric Christopher
1e6f9b376b Remove the need to cache the subtarget in the X86 TargetRegisterInfo
classes. Use a Triple instead and simplify a lot of the querying
logic to use lookups on the Triple.

llvm-svn: 232071
2015-03-12 17:54:19 +00:00
Krzysztof Parzyszek
49d1e29261 Remove unused complex patterns for addressing modes on Hexagon.
llvm-svn: 232057
2015-03-12 16:44:50 +00:00
Sanjay Patel
627c8ecb2b make an array of constants explicitly const
Suggested by Craig Topper in D8184.

This goes with r232047.

llvm-svn: 232056
2015-03-12 16:29:58 +00:00
Sanjay Patel
1912cfcc7b IRBuilder: add a CreateShuffleVector function that takes an ArrayRef of int
This is a convenience function to ease mask creation of ShuffleVectors
in AutoUpgrade and other places.

Differential Revision: http://reviews.llvm.org/D8184

llvm-svn: 232047
2015-03-12 15:27:07 +00:00
Andrea Di Biagio
b58c185f5a [X86] Fix wrong target specific combine on SETCC nodes.
Part of the folding logic implemented by function 'PerformISDSETCCCombine'
only worked under the assumption that the condition code in input could have
been either SETNE or SETEQ.
Unfortunately that assumption was incorrect, and in some cases the algorithm
ended up incorrectly folding SETCC nodes.

The incorrect folding only affected SETCC dag nodes where:
 - one of the operands was a build_vector of all zeroes;
 - the other operand was a SIGN_EXTEND from a vector of MVT:i1 elements;
 - the condition code was neither SETNE nor SETEQ.

Example:
  (setcc (v4i32 (sign_extend v4i1:%A)), (v4i32 VectorOfAllZeroes), setge)

Before this patch, the entire dag node sequence from the example was
incorrectly folded to node %A.

With this patch, the dag node sequence is folded to a
  (xor %A, (v4i1 VectorOfAllOnes)).

Added test setcc-combine.ll.

Thanks to Greg Bedwell for spotting this issue.

llvm-svn: 232046
2015-03-12 15:16:58 +00:00
Sanjay Patel
aa9ea9aae7 [X86, AVX] replace vextractf128 intrinsics with generic shuffles
Now that we've replaced the vinsertf128 intrinsics, 
do the same for their extract twins.

This is very much like D8086 (checked in at r231794):
We want to replace as much custom x86 shuffling via intrinsics
as possible because pushing the code down the generic shuffle
optimization path allows for better codegen and less complexity
in LLVM.

This is also the LLVM sibling to the cfe D8275 patch.

Differential Revision: http://reviews.llvm.org/D8276

llvm-svn: 232045
2015-03-12 15:15:19 +00:00
Aaron Ballman
83e74ee34d Silencing an "enumeral and non-enumeral type in conditional expression" warning; NFC.
llvm-svn: 232035
2015-03-12 13:24:06 +00:00
Daniel Sanders
4eee6f840d Add infrastructure for support of multiple memory constraints.
Summary:
The operand flag word for ISD::INLINEASM nodes now contains a 15-bit
memory constraint ID when the operand kind is Kind_Mem. This constraint
ID is a numeric equivalent to the constraint code string and is converted
with a target specific hook in TargetLowering.

This patch maps all memory constraints to InlineAsm::Constraint_m so there
is no functional change at this point. It just proves that using these
previously unused bits in the encoding of the flag word doesn't break anything.

The next patch will make each target preserve the current mapping of
everything to Constraint_m for itself while changing the target independent
implementation of the hook to return Constraint_Unknown appropriately. Each
target will then be adapted in separate patches to use appropriate Constraint_*
values.

Reviewers: hfinkel

Reviewed By: hfinkel

Subscribers: hfinkel, jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D8171

llvm-svn: 232027
2015-03-12 11:00:48 +00:00
Elena Demikhovsky
e21b4ac3e7 AVX-512: Added encoding tests for VPROR, VPROL instructions,
fixed opcode.

llvm-svn: 232018
2015-03-12 07:28:41 +00:00
Eric Christopher
84c7b275d4 Remove some unnecessary forward declarations and put a couple more
where they're supposed to reside.

llvm-svn: 232014
2015-03-12 06:07:16 +00:00
Eric Christopher
6fdf45075c Remove the need to cache the subtarget in the Sparc TargetRegisterInfo
classes.

llvm-svn: 232013
2015-03-12 05:55:26 +00:00
Eric Christopher
5c14e6461d Remove the need to cache the subtarget in the Mips TargetRegisterInfo
classes.

llvm-svn: 232012
2015-03-12 05:43:57 +00:00
Kevin Qin
5fb79c9e03 Reapply 'Run LICM pass after loop unrolling pass.'
It's firstly committed at r231630, and reverted at r231635.

Function pass InstructionSimplifier is inserted as barrier to
make sure loop unroll pass won't affect on LICM pass.

llvm-svn: 232011
2015-03-12 05:36:01 +00:00
Eric Christopher
4b1f61b9bc Remove the need to cache the subtarget in the ARM TargetRegisterInfo
classes. Replace the frame pointer initialization with a static function
that'll look it up via the subtarget on the MachineFunction.

llvm-svn: 232010
2015-03-12 05:12:31 +00:00
Eric Christopher
2dfd900346 Remove the need to cache the subtarget in the AArch64 TargetRegisterInfo
classes. Replace it with a cache to the Triple and use that
where applicable at the moment.

llvm-svn: 232005
2015-03-12 02:04:46 +00:00
Jingyue Wu
764ac5a7c6 [NVPTXAsmPrinter] do not print .align on function headers
Summary:
PTX does not allow .align directives on function headers.

Fixes PR21551.

Test Plan: test/Codegen/NVPTX/function-align.ll

Reviewers: eliben, jholewinski

Reviewed By: eliben, jholewinski

Subscribers: llvm-commits, eliben, jpienaar, jholewinski

Differential Revision: http://reviews.llvm.org/D8274

llvm-svn: 232004
2015-03-12 01:50:30 +00:00
Reid Kleckner
ae151db0a9 Make llvm.eh.actions an intrinsic and add docs for it
These docs *don't* match the way WinEHPrepare uses them yet, and
verifier support isn't implemented either. The implementation will come
after the documentation text is reviewed and agreed upon.

llvm-svn: 232003
2015-03-12 01:45:37 +00:00
Eric Christopher
15706e9593 Remove the need to cache the subtarget in the PowerPC TargetRegisterInfo
classes. Replace it with a cache to the TargetMachine and use that
where applicable at the moment.

llvm-svn: 232002
2015-03-12 01:42:51 +00:00
Krzysztof Parzyszek
445e825bfd Fix build break introduced in r231992
llvm-svn: 231996
2015-03-12 00:49:13 +00:00
Reid Kleckner
997aab28ac Stop calling DwarfEHPrepare from WinEHPrepare
Instead, run both EH preparation passes, and have them both ignore
functions with unrecognized EH personalities. Pass delegation involved
some hacky code for creating an AnalysisResolver that we don't need now.

llvm-svn: 231995
2015-03-12 00:36:20 +00:00
Krzysztof Parzyszek
62f208b598 Eliminate constant-extender profitability checks from Hexagon isel
llvm-svn: 231992
2015-03-12 00:19:59 +00:00
Mehdi Amini
94c8770ed5 Move the DataLayout to the generic TargetMachine, making it mandatory.
Summary:
I don't know why every singled backend had to redeclare its own DataLayout.
There was a virtual getDataLayout() on the common base TargetMachine, the
default implementation returned nullptr. It was not clear from this that
we could assume at call site that a DataLayout will be available with
each Target.

Now getDataLayout() is no longer virtual and return a pointer to the
DataLayout member of the common base TargetMachine. I plan to turn it into
a reference in a future patch.

The only backend that didn't have a DataLayout previsouly was the CPPBackend.
It now initializes the default DataLayout. This commit is NFC for all the
other backends.

Test Plan: clang+llvm ninja check-all

Reviewers: echristo

Subscribers: jfb, jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D8243

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 231987
2015-03-12 00:07:24 +00:00
Reid Kleckner
49cd81f1f5 Fix some clang warnings in WinEHPrepare
llvm-svn: 231985
2015-03-11 23:39:36 +00:00
Reid Kleckner
789a64e429 Handle big index in getelementptr instruction
CodeGen incorrectly ignores (assert from APInt) constant index bigger
than 2^64 in getelementptr instruction. This is a test and fix for that.

Patch by Paweł Bylica!

Reviewed By: rnk

Subscribers: majnemer, rnk, mcrosier, resistor, llvm-commits

Differential Revision: http://reviews.llvm.org/D8219

llvm-svn: 231984
2015-03-11 23:36:10 +00:00
Hal Finkel
0e0ffffd14 [PowerPC] Remove canFoldAsLoad from instruction definitions
The PowerPC backend had a number of loads that were marked as canFoldAsLoad
(and I'm partially at fault here for copying around the relevant line of
TableGen definitions without really looking at what it meant). This is not
right; PPC (non-memory) instructions don't support direct memory operands, and
so there is nothing a 'foldable' instruction could be folded into.

Noticed by inspection, no test case.

The one thing we might lose by doing this is ability to fold some loads into
stackmap/patchpoint pseudo-instructions. However, this was untested, and would
not obviously have worked for extending loads, and I'd rather re-add support
for that once it can be tested.

llvm-svn: 231982
2015-03-11 23:28:38 +00:00
Andrew Kaylor
6bed959c78 Extended support for native Windows C++ EH outlining
Differential Review: http://reviews.llvm.org/D7886

llvm-svn: 231981
2015-03-11 23:22:06 +00:00
Eric Christopher
b5d16a61c0 Remove useMachineScheduler and replace it with subtarget options
that control, individually, all of the disparate things it was
controlling.

At the same time move a FIXME in the Hexagon port to a new
subtarget function that will enable a user of the machine
scheduler to avoid using the source scheduler for pre-RA-scheduling.
The FIXME would have this removed, but involves either testcase
changes or adding -pre-RA-sched=source to a few testcases.

llvm-svn: 231980
2015-03-11 22:56:10 +00:00
Eric Christopher
7e02765bdf Have getCallPreservedMask and getThisCallPreservedMask take a
MachineFunction argument so that we can grab subtarget specific
features off of it.

llvm-svn: 231979
2015-03-11 22:42:13 +00:00
Eric Christopher
bb8d7dfb81 One more getCalleeSavedRegs prototype with nullptr.
llvm-svn: 231977
2015-03-11 22:24:37 +00:00
Eric Christopher
32ae945f51 Have getCalleeSavedRegs take a non-null MachineFunction all the
time. The target independent code was passing in one all the
time and targets weren't checking validity before using. Update
a few calls to pass in a MachineFunction where necessary.

llvm-svn: 231970
2015-03-11 21:41:28 +00:00
Pete Cooper
1a6a1af22a Constify AArch64CollectLOH.cpp. NFC
llvm-svn: 231969
2015-03-11 21:40:25 +00:00
Jozef Kolek
3f22787f2e [mips][microMIPS] Make usage of NOT16 by code generator
Differential Revision: http://reviews.llvm.org/D7748

llvm-svn: 231963
2015-03-11 20:28:31 +00:00
Rafael Espindola
268252825b Put jump tables in unique sections on COFF.
If a function is going in an unique section (because of -ffunction-sections
for example), putting a jump table in .rodata will keep .rodata alive and
that will keep alive any other function that also has a jump table.

Instead, put the jump table in a unique section that is associated with the
function.

llvm-svn: 231961
2015-03-11 19:58:37 +00:00
Tim Northover
5e9ed07177 ARM: simplify and extend byval handling
The main issue being fixed here is that APCS targets handling a "byval align N"
parameter with N > 4 were miscounting what objects were where on the stack,
leading to FrameLowering setting the frame pointer incorrectly and clobbering
the stack.

But byval handling had grown over many years, and had multiple layers of cruft
trying to compensate for each other and calculate padding correctly. This only
really needs to be done once, in the HandleByVal function. Elsewhere should
just do what it's told by that call.

I also stripped out unnecessary APCS/AAPCS distinctions (now that Clang emits
byvals with the correct C ABI alignment), which simplified HandleByVal.

rdar://20095672

llvm-svn: 231959
2015-03-11 18:54:22 +00:00
Eric Christopher
e162768309 Remove the need to cache the subtarget in the R600 TargetRegisterInfo
classes.

llvm-svn: 231954
2015-03-11 18:43:21 +00:00
Eric Christopher
2925153548 Have getRegPressureSetLimit take a MachineFunction so that a
we can inspect the subtarget and function when computing values.

llvm-svn: 231951
2015-03-11 18:34:58 +00:00
David Majnemer
613caa1eaa InstCombine: Don't fold call bitcast into args if callee is byval
This fixes a bug reported here:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20150309/265341.html

llvm-svn: 231948
2015-03-11 18:03:05 +00:00
Kit Barton
cd4d15759a Updated with list of possible improvements we are tracking internally
llvm-svn: 231946
2015-03-11 17:43:43 +00:00
Juergen Ributzka
f7fcca505b Add the "vbroadcasti128" instruction back.
This is a follow-up to r231182. This adds the "vbroadcasti128" instruction
back, but without the intrinsic mapping. Also add a test to check the
instriction encoding.

This is related to rdar://problem/18742778.

llvm-svn: 231945
2015-03-11 17:29:03 +00:00
Derek Schuff
5d3b63bf2e Make NaCl's use of .init_array for static constructors match Linux
Summary:
The generic ELF TargetObjectFile defaults to .ctors, but Linux's
defaults to .init_array by calling InitializeELF with the value of
UseInitArray from TargetMachine. Make NaCl's behavior match.

Reviewers: jvoung
Differential Revision: http://reviews.llvm.org/D8240

llvm-svn: 231934
2015-03-11 16:16:09 +00:00
Benjamin Kramer
2540a3451e Wrap in __MINGW32__ to avoid warnings from msvc.
llvm-svn: 231933
2015-03-11 16:09:02 +00:00
Benjamin Kramer
7b9e4d7ca3 Add missing namespace specifier for MSVC.
llvm-svn: 231930
2015-03-11 15:53:24 +00:00
Benjamin Kramer
b7e47cc28e RtlCaptureContext is absent from the mingw32 headers, provide a prototype.
llvm-svn: 231929
2015-03-11 15:41:15 +00:00
Sanjay Patel
f8b6a29222 Inliner should not add callgraph edges for intrinsic calls (PR22857)
The CallGraphNode function "addCalledFunction()" asserts that edges are not to intrinsics.

This patch makes sure that the Inliner does not add such an edge to the callgraph.

Fix for clang crash by assertion: https://llvm.org/bugs/show_bug.cgi?id=22857

Differential Revision: http://reviews.llvm.org/D8231

llvm-svn: 231927
2015-03-11 15:12:32 +00:00
Elena Demikhovsky
320252ae4d AVX-512: Added SKX forms of shift instructions.
Added rotation instructions, encoding only.
Added encoding tests for all these forms.

llvm-svn: 231916
2015-03-11 10:25:42 +00:00
Owen Anderson
018886831b Fix another verifier crash where a GC intrinsic would look at the internals of another intrinsic in order to verify itself.
This causes a crash if the referenced intrinsic was malformed.  In this case, we
would already have reported an error on the referenced intrinsic, but then
crashed on the second one when it tried to introspect the first without
error checking.

llvm-svn: 231910
2015-03-11 06:57:30 +00:00
Rafael Espindola
4ef6243723 Don't print labels that on ELF are never used.
llvm-svn: 231904
2015-03-11 04:20:31 +00:00
Justin Bogner
ba70a38423 InstrProf: Teach llvm-cov to handle universal binaries when given -arch
llvm-svn: 231902
2015-03-11 02:30:51 +00:00
Rafael Espindola
6932b2f8e9 Print section start labels when first switching to the section.
This is less brittle and avoids polluting the start of the file with every
debug section.

llvm-svn: 231898
2015-03-11 00:51:37 +00:00