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3 Commits

Author SHA1 Message Date
Ehsan Amiri
db43217a24 Adding -verify-machineinstrs option to PowerPC tests 
Currently we have a number of tests that fail with -verify-machineinstrs.
To detect this cases earlier we add the option to the testcases with the
exception of tests that will currently fail with this option. PR 27456 keeps
track of this failures.

No code review, as discussed with Hal Finkel.

llvm-svn: 277624
 2016-08-03 18:17:35 +00:00
Kit Barton
f514e1c5fc Change the generation of the vmuluwm instruction to be based on the MUL opcode. 
Phabricator review: http://reviews.llvm.org/D8185

llvm-svn: 231827
 2015-03-10 19:49:38 +00:00
Kit Barton
2e98937142 Add the following 64-bit vector integer arithmetic instructions added in POWER8: 
vaddudm
vsubudm
vmulesw
vmulosw
vmuleuw
vmulouw
vmuluwm
vmaxsd
vmaxud
vminsd
vminud
vcmpequd
vcmpequd.
vcmpgtsd
vcmpgtsd.
vcmpgtud
vcmpgtud.
vrld
vsld
vsrd
vsrad

Phabricator review: http://reviews.llvm.org/D7959

llvm-svn: 231115
 2015-03-03 19:55:45 +00:00