Evan Cheng
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abcf3842bb
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Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
llvm-svn: 38501
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2007-07-10 18:08:01 +00:00 |
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Evan Cheng
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d9d3be078c
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No need for ccop anymore.
llvm-svn: 37965
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2007-07-06 23:34:09 +00:00 |
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Evan Cheng
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ef8a1bcbc3
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Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.
llvm-svn: 37895
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2007-07-05 07:13:32 +00:00 |
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Evan Cheng
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7b433a2954
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Mark these instructions clobbersPred. They modify the condition code register.
llvm-svn: 37468
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2007-06-06 10:17:05 +00:00 |
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Evan Cheng
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3672d15956
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For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias.
llvm-svn: 37351
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2007-05-29 23:34:19 +00:00 |
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Evan Cheng
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9f0ffdf4b3
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Add PredicateOperand to all ARM instructions that have the condition field.
llvm-svn: 37066
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2007-05-15 01:29:07 +00:00 |
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Evan Cheng
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73abcaa525
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Switch BCC, MOVCCr, etc. to PredicateOperand.
llvm-svn: 36948
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2007-05-08 21:08:43 +00:00 |
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Evan Cheng
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a949d165ee
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This is no longer needed after enabling the DAG combiner xform.
llvm-svn: 36909
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2007-05-07 21:29:41 +00:00 |
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Dale Johannesen
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d28d0bac2a
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Evan's patch to avoid FPreg->intreg copy for cvt; store to mem
llvm-svn: 36693
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2007-05-03 20:54:42 +00:00 |
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Chris Lattner
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844e3a4191
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match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll
llvm-svn: 36660
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2007-05-03 00:32:00 +00:00 |
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Evan Cheng
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c6e1d453d3
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ARM backend contribution from Apple.
llvm-svn: 33353
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2007-01-19 07:51:42 +00:00 |
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