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Commit Graph

71443 Commits

Author SHA1 Message Date
Joerg Sonnenberger
abd973f309 mbar without argument is equivalent to mbar 0.
llvm-svn: 214250
2014-07-29 23:31:27 +00:00
Duncan P. N. Exon Smith
cc8a88fa18 Revert "UseListOrder: Order GlobalValue uses after initializers"
This reverts commits r214242 and r214243 while I investigate buildbot
failures [1][2][3].  I can't reproduce these failures locally, so if
anyone can see what I've done wrong, I'd appreciate a note.

[1]: http://lab.llvm.org:8011/builders/llvm-hexagon-elf/builds/9840
[2]: http://lab.llvm.org:8011/builders/clang-hexagon-elf/builds/14981
[3]: http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/15191

llvm-svn: 214249
2014-07-29 23:31:11 +00:00
Joerg Sonnenberger
afb8bfcb47 Recognize BookE's mbar instruction.
llvm-svn: 214244
2014-07-29 23:16:31 +00:00
Duncan P. N. Exon Smith
cdab8367f8 UseListOrder: Order GlobalValue uses after initializers
To avoid unnecessary forward references, the reader doesn't process
initializers of `GlobalValue`s until after the constant pool has been
processed, and then in reverse order.  Model this when predicting
use-list order.  This gets two more Bitcode tests passing with
`llvm-uselistorder`.

Part of PR5680.

llvm-svn: 214242
2014-07-29 23:06:14 +00:00
Duncan P. N. Exon Smith
589a519a8a UseListOrder: Create a struct around OrderMap, NFC
llvm-svn: 214241
2014-07-29 23:03:40 +00:00
Manman Ren
d130fd7e21 Feedback on r214189, no functionality change.
llvm-svn: 214240
2014-07-29 22:58:13 +00:00
Joerg Sonnenberger
5dd0828a9c Fix typo in alias: DSIR -> DSISR
llvm-svn: 214238
2014-07-29 22:42:44 +00:00
Justin Bogner
6ed5e5948b llvm-profdata: Clean up and reorganize some tests
This moves some tests around to make it clearer what's being tested,
and adds very rudimentary comment syntax to the text input format to
make specifying this kind of test a little bit simpler.

llvm-svn: 214235
2014-07-29 22:29:23 +00:00
Joerg Sonnenberger
d52d4c80b5 Support move to/from segment register.
llvm-svn: 214234
2014-07-29 22:21:57 +00:00
Alex Lorenz
9503511918 Coverage: improve efficiency of the counter propagation to the expansion regions.
This patch reduces the complexity of the two inner loops in order to speed up 
the loading of coverage data for very large functions.

llvm-svn: 214228
2014-07-29 21:42:24 +00:00
Lang Hames
1d332e5199 [MCJIT] Make sure we print the full 64-bit result of exprs in RuntimeDyldChecker.
llvm-svn: 214227
2014-07-29 21:38:20 +00:00
Matt Arsenault
ccbab61a53 R600/SI: Implement getLdStBaseRegImmOfs
llvm-svn: 214225
2014-07-29 21:34:55 +00:00
Rafael Espindola
74ac2cd9f3 Have a single enum for "not a bitcode" error.
This is more convenient for callers. No functionality change, this will
be used in a next patch to the gold plugin.

llvm-svn: 214218
2014-07-29 21:01:24 +00:00
Matt Arsenault
d64b11dc6c R600/SI: Enable named operand table for DS instructions
llvm-svn: 214217
2014-07-29 21:00:56 +00:00
Matt Arsenault
5d4212bf5b Remove line with no effect
llvm-svn: 214216
2014-07-29 21:00:53 +00:00
Lang Hames
46768ed40a [MCJIT] Make the RuntimeDyldChecker stub_addr builtin use file names rather than
full paths for its first argument.

This allows us to remove the annoying sed lines in the test cases, and write
direct references to file names in stub_addr calls (rather than <filename>
placeholders).

llvm-svn: 214211
2014-07-29 20:40:37 +00:00
Rafael Espindola
06b2000418 Move the bitcode error enum to the include directory.
This will let users in other libraries know which error occurred. In particular,
it will be possible to check if the parsing failed or if the file is not
bitcode.

llvm-svn: 214209
2014-07-29 20:22:46 +00:00
Alex Lorenz
7522b90640 Coverage: fix the missing output stream in recursive call to CoverageMappingContext::dump
llvm-svn: 214206
2014-07-29 19:58:16 +00:00
Juergen Ributzka
2fe879698c [RuntimeDyld][AArch64] Make encode/decodeAddend also work on big-endian hosts.
llvm-svn: 214205
2014-07-29 19:57:15 +00:00
Juergen Ributzka
53d208d4b9 [RuntimeDyld][AArch64] Make encode/decodeAddend more typesafe by using the relocation enum type. NFCI.
llvm-svn: 214204
2014-07-29 19:57:11 +00:00
Joerg Sonnenberger
f3709585f9 Add a number of aliases for SPR access.
llvm-svn: 214196
2014-07-29 18:55:43 +00:00
Matt Arsenault
001ee9417a R600/SI: Add isMUBUF / isMTBUF
Also add missing comments about how the flags work.

llvm-svn: 214195
2014-07-29 18:51:56 +00:00
Matt Arsenault
751b041f67 R600/SI: Set bits on SMRD instructions
Set mayStore = 0 and enable named operand table.

llvm-svn: 214194
2014-07-29 18:51:54 +00:00
Manman Ren
647e271afe [Debug Info] remove DITrivialType and use null to represent unspecified param.
Per feedback on r214111, we are going to use null to represent unspecified
parameter. If the type array is {null}, it means a function that returns void;
If the type array is {null, null}, it means a variadic function that returns
void. In summary if we have more than one element in the type array and the last
element is null, it is a variadic function.

rdar://17628609

llvm-svn: 214189
2014-07-29 18:20:39 +00:00
Duncan P. N. Exon Smith
8013451450 IR: Create the use-list order shuffle vector in-place
Per David Blaikie's review of r214135, this is a more natural way to
initialize.

llvm-svn: 214184
2014-07-29 16:58:18 +00:00
Joerg Sonnenberger
c3bec0cdc8 Add rfi instruction. Based on feedback by Ulrich Weigand.
llvm-svn: 214181
2014-07-29 15:49:09 +00:00
Sasa Stankovic
28de54fc38 [mips] Don't use odd-numbered single precision registers for fastcc calling
convention if -mno-odd-spreg is used.

Differential Revision: http://reviews.llvm.org/D4682

llvm-svn: 214180
2014-07-29 14:39:24 +00:00
Tim Northover
2329ee9f83 CodeGenPrep: fall back to MVT::Other if instruction's type isn't an EVT.
The test being performed is just an approximation anyway, so it really
shouldn't crash when things don't go entirely as expected.

Should fix PR20474.

llvm-svn: 214177
2014-07-29 10:20:22 +00:00
Tim Northover
d84d65ed82 ARM: add __aeabi_d2h for truncation on AEABI systems
ARM does actually define the name for this conversion, so we should use it on
"-eabi" platforms.

llvm-svn: 214176
2014-07-29 09:56:45 +00:00
Tim Northover
3913b2ef67 ARM: fix @llvm.convert.from.fp16 on softfloat targets.
We need to make sure we use the softened version of all appropriate operands in
the libcall, or things go horribly wrong. This may entail actually executing a
1-stage softening.

llvm-svn: 214175
2014-07-29 09:56:38 +00:00
Jiangning Liu
86fc448354 Implement AArch64 TTI interface isAsCheapAsAMove.
llvm-svn: 214159
2014-07-29 02:09:26 +00:00
Jiangning Liu
aec69df4ca Add TargetInstrInfo interface isAsCheapAsAMove.
llvm-svn: 214158
2014-07-29 01:55:19 +00:00
Duncan P. N. Exon Smith
a47a95e521 Bitcode: Correctly compare a Use against itself
Fix the sort of expected order in the reader to correctly return `false`
when comparing a `Use` against itself.

This was caught by test/Bitcode/binaryIntInstructions.3.2.ll, so I'm
adding a `RUN` line using `llvm-uselistorder` for every test in
`test/Bitcode` that passes.

A few tests still fail, so I'll investigate those next.

This is part of PR5680.

llvm-svn: 214157
2014-07-29 01:13:56 +00:00
Duncan P. N. Exon Smith
4936d185e0 IR: Augment debug statements for use-list order
llvm-svn: 214155
2014-07-29 01:09:46 +00:00
Matt Arsenault
55d94a2290 Fix typos / grammar.
llvm-svn: 214147
2014-07-29 00:02:40 +00:00
Matt Arsenault
8eaa31c417 Fix header including itself
llvm-svn: 214146
2014-07-29 00:02:37 +00:00
Manman Ren
c36c9cb0ea [Debug Info] unique MDNodes in the enum types of each compile unit.
The enum types array by design contains pointers to MDNodes rather than DIRefs.
Unique them when handling the enum types in DwarfDebug.

rdar://17628609

llvm-svn: 214139
2014-07-28 23:04:20 +00:00
Duncan P. N. Exon Smith
ef82c1e632 IR: Optimize size of use-list order shuffle vectors
Since we're storing lots of these, save two-pointers per vector with a
custom type rather than using the relatively heavy `SmallVector`.

Part of PR5680.

llvm-svn: 214135
2014-07-28 22:41:50 +00:00
Manman Ren
3a8334cabf [Debug Info] add DISubroutineType and its creation takes DITypeArray.
DITypeArray is an array of DITypeRef, at its creation, we will create
DITypeRef (i.e use the identifier if the type node has an identifier).

This is the last patch to unique the type array of a subroutine type.

rdar://17628609

llvm-svn: 214132
2014-07-28 22:24:06 +00:00
Duncan P. N. Exon Smith
1ad861d158 Bitcode: Serialize (and recover) use-list order
Predict and serialize use-list order in bitcode.  This makes the option
`-preserve-bc-use-list-order` work *most* of the time, but this is still
experimental.

  - Builds a full value-table up front in the writer, sets up a list of
    use-list orders to write out, and discards the table.  This is a
    simpler first step than determining the order from the various
    overlapping IDs of values on-the-fly.

  - The shuffles stored in the use-list order list have an unnecessarily
    large memory footprint.

  - `blockaddress` expressions cause functions to be materialized
    out-of-order.  For now I've ignored this problem, so use-list orders
    will be wrong for constants used by functions that have block
    addresses taken.  There are a couple of ways to fix this, but I
    don't have a concrete plan yet.

  - When materializing functions lazily, the use-lists for constants
    will not be correct.  This use case is out of scope: what should the
    use-list order be, if it's incomplete?

This is part of PR5680.

llvm-svn: 214125
2014-07-28 21:19:41 +00:00
Manman Ren
65af793195 [Debug Info] add a template class DITypedArray.
Typedef DIArray to DITypedArray<DIDescriptor>. Also typedef DITypeArray as
DITypedArray<DITypeRef>.

This is the third of a series of patches to handle type uniqueing of the
type array for a subroutine type.

This commit should have no functionality change.

llvm-svn: 214115
2014-07-28 19:33:20 +00:00
Manman Ren
b786c25f5b [Debug Info] rename getTypeArray to getElements, setTypeArray to setArrays.
This is the second of a series of patches to handle type uniqueing of the
type array for a subroutine type.

For vector and array types, getElements returns the array of subranges, so it
is a better name than getTypeArray. Even for class, struct and enum types,
getElements returns the members, which can be subprograms.

setArrays can set up to two arrays, the second is the templates.

This commit should have no functionality change.

llvm-svn: 214112
2014-07-28 19:14:13 +00:00
Manman Ren
7d984c2709 [Debug Info] replace DIUnspecifiedParameter with DITrivialType.
This is the first of a series of patches to handle type uniqueing of the
type array for a subroutine type.

This commit makes sure unspecified_parameter is a DIType to enable converting
the type array for a subroutine type to an array of DITypes.

This commit should have no functionality change. With this commit, we may
change unspecified type to be a DITrivialType instead of a DIType.

llvm-svn: 214111
2014-07-28 18:52:30 +00:00
Matt Arsenault
feabef83e1 R600/SI: Fix return type for isMIMG / isSMRD
All the others use bool, so these should too.

llvm-svn: 214106
2014-07-28 17:59:38 +00:00
Chandler Carruth
4123a2c212 [SDAG] Add DEBUG logging to the legalizer, fixing a "bug" found by
inspection in the proccess, and shuffle the logging in the DAG combiner
around a bit.

With this it is much easier to follow what the legalizer is doing. It
should even accurately present most of the strange legalization
operations where a single node is replaced by multiple nodes, etc. There
is still some information lost (we log SDNodes not SDValues so we don't
log which result is used for which thing), but I think this is much
closer to a usable system. Notably, this will make it *much* more
apparant when legalization is actually happening inside the combiner, or
when there is a cycle caused by interactions of the legalizer and the
combiner.

The "bug" I fixed here I'm not sure is remotely possible to trigger. We
were only adding one of the nodes in a replacement to the updated set
rather than all of the nodes in the replacement. Realistically, the
worst result of this are nodes not getting back onto the worklist in the
DAG combiner. I doubt it is possible to trigger this today, and
I certainly don't have any ideas about how, but this at least brings the
code into alignment with the principled operation of the routine.

llvm-svn: 214105
2014-07-28 17:55:07 +00:00
Matt Arsenault
1c1d6d00fc R600/SI: Implement getOptimalMemOpType
The default guess uses i32. This needs an address space argument
to really do the right thing in all cases.

llvm-svn: 214104
2014-07-28 17:49:26 +00:00
Matt Arsenault
ba2df7591d R600/SI: Make argument loads invariant
llvm-svn: 214101
2014-07-28 17:31:39 +00:00
Robert Khasanov
d86d770d47 [SKX] Enabling mask logic instructions: encoding, lowering
Instructions: KAND{BWDQ}, KANDN{BWDQ}, KOR{BWDQ}, KXOR{BWDQ}, KXNOR{BWDQ}

Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>

llvm-svn: 214081
2014-07-28 13:46:45 +00:00
Ulrich Weigand
37cf88e787 [PowerPC] Support ELFv1/ELFv2 ABI selection via features
While LLVM now supports both ELFv1 and ELFv2 ABIs, their use is currently
hard-coded via the target triple: powerpc64-linux is always ELFv1, while
powerpc64le-linux is always ELFv2.

These are of course the most common scenarios, but in principle it is
possible to support the ELFv2 ABI on big-endian or the ELFv1 ABI on
little-endian systems (and GCC does support that), and there are some
special use cases for that (e.g. certain Linux kernel versions could
only be built using ELFv1 on LE).

This patch implements the LLVM side of supporting this.  As precedent
on other platforms suggests, ABI options are passed to the back-end as
features.  Thus, this patch implements two features "elfv1" and "elfv2"
that select the desired ABI if present.  (If not, the LLVM uses the
same default rules as now.)

llvm-svn: 214072
2014-07-28 13:09:28 +00:00
Saleem Abdulrasool
a8620ea425 ARM: correct handling of features in arch_extension
The subtarget information is the ultimate source of truth for the feature set
that is enabled at this point.  We would previously not propagate the feature
information to the subtarget.  While this worked for the most part (features
would be enabled/disabled as requested), if another operation that changed the
feature bits was encountered (such as a mode switch via a .arm or .thumb
directive), we would end up resetting the behaviour of the architectural
extensions.

Handling this properly requires a slightly more complicated handling.  We need
to check if the feature is now being toggled.  If so, only then do we toggle the
features.  In return, we no longer have to calculate the feature bits ourselves.

The test changes are mostly to the diagnosis, which is now more uniform (a nice
side effect!).  Add an additional test to ensure that we handle this case
properly.

Thanks to Nico Weber for alerting me to this issue!

llvm-svn: 214057
2014-07-27 19:07:09 +00:00