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Commit Graph

156731 Commits

Author SHA1 Message Date
Matt Arsenault
eaea634604 AMDGPU: Select d16 loads into low component of register
llvm-svn: 318005
2017-11-13 00:22:09 +00:00
Matt Arsenault
d9c8715837 AMDGPU: Fix -enable-var-scope violations
llvm-svn: 318004
2017-11-12 23:53:44 +00:00
Matt Arsenault
d207bf89ab AMDGPU: Fix missing gfx9 atomic inc/dec tests
The global instructions weren't tested. Plus there
were also some -enable-var-scope violations and
broken check prefixes.

llvm-svn: 318003
2017-11-12 23:40:12 +00:00
Craig Topper
45210b7de6 [X86] Add an X86ISD::RANGES opcode to use for the scalar intrinsics.
This fixes a bug where we selected packed instructions for scalar intrinsics.

llvm-svn: 317999
2017-11-12 18:51:09 +00:00
Craig Topper
cc2b32a675 [X86] Add test cases and command lines demonstrating how we accidentally select vrangeps/vrangepd from vrangess/vrangesd instrinsics when the rounding mode is CUR_DIRECTION
llvm-svn: 317998
2017-11-12 18:51:08 +00:00
Craig Topper
bc3b5e9708 [X86] Remove some no longer needed intrinsic lowering code.
llvm-svn: 317997
2017-11-12 18:51:06 +00:00
Mandeep Singh Grang
32947f7b72 [llvm] Remove redundant return [NFC]
Reviewers: davidxl, olista01, Eugene.Zelenko

Reviewed By: Eugene.Zelenko

Subscribers: sdardis, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D39917

llvm-svn: 317995
2017-11-12 03:47:50 +00:00
Craig Topper
6dbd706f89 [InstCombine] Teach visitICmpInst to not break integer absolute value idioms
Summary:
This patch adds an early out to visitICmpInst if we are looking at a compare as part of an integer absolute value idiom. Similar is already done for min/max.

In the particular case I observed in a benchmark we had an absolute value of a load from an indexed global. We simplified the compare using foldCmpLoadFromIndexedGlobal into a magic bit vector, a shift, and an and. But the load result was still used for the select and the negate part of the absolute valute idiom. So we overcomplicated the code and lost the ability to recognize it as an absolute value.

I've chosen a simpler case for the test here.

Reviewers: spatel, davide, majnemer

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D39766

llvm-svn: 317994
2017-11-12 02:28:21 +00:00
Craig Topper
d9e3d1df1d [X86] Use vrndscaleps/pd for 128/256 ffloor/ftrunc/fceil/fnearbyint/frint when avx512vl is enabled.
This matches what we do for scalar and 512-bit types.

llvm-svn: 317991
2017-11-11 21:44:51 +00:00
Craig Topper
807c3846c6 [X86] Remove avx512-round.ll. The 512-bit rounding tests are now in vec_floor.ll with 128/256 sizes.
llvm-svn: 317990
2017-11-11 21:44:50 +00:00
Craig Topper
d9337d8964 [X86] Add avx512vl command line to vec_floor.ll. Add 512-bit test cases.
llvm-svn: 317989
2017-11-11 21:44:49 +00:00
Craig Topper
389a205040 [X86] Add avx512f command line to rounding-ops.ll
llvm-svn: 317988
2017-11-11 21:44:48 +00:00
Craig Topper
3a3c977330 [X86] Regenerate rounding-ops.ll with update_llc_test_checks.py
llvm-svn: 317987
2017-11-11 21:44:47 +00:00
Simon Pilgrim
ca9ad6eb90 [X86] Attempt to match multiple binary reduction ops at once. NFCI
matchBinOpReduction currently matches against a single opcode, but we already have a case where we repeat calls to try to match against AND/OR and I'll be shortly adding another case for SMAX/SMIN/UMAX/UMIN (D39729).

This NFCI patch alters matchBinOpReduction to try and pattern match against any of the provided list of candidate bin ops at once to save time.

Differential Revision: https://reviews.llvm.org/D39726

llvm-svn: 317985
2017-11-11 18:16:55 +00:00
Craig Topper
1561471af3 [X86] Add scalar register class versions of VRNDSCALE instructions and rename the existing versions to _Int.
This is consistent with out normal implementation of scalar instructions.

While there disable load folding for the patterns with IMPLICIT_DEF unless optimizing for size which is also our standard practice.

llvm-svn: 317977
2017-11-11 08:24:15 +00:00
Craig Topper
f495c94083 [X86] Regenerate avx512-round.ll test.
llvm-svn: 317976
2017-11-11 08:24:13 +00:00
Craig Topper
b00f777f2d [X86] Inline some SDNode operand multiclass operands that don't vary. NFC
llvm-svn: 317975
2017-11-11 08:24:12 +00:00
Craig Topper
1828639ac4 [X86] Set the execution domain for VFPCLASS to SSEPackedSingle/Double.
llvm-svn: 317974
2017-11-11 06:57:44 +00:00
Craig Topper
afb6899bc5 [X86] Set the execution domain for vptest instruction to the integer domain.
llvm-svn: 317973
2017-11-11 06:19:12 +00:00
Daniel Sanders
45f30d3e9a [globalisel][tablegen] Import signextload and zeroextload.
Allow a pattern rewriter to be installed in CodeGenDAGPatterns and use it to
correct situations where SelectionDAG and GlobalISel disagree on
representation. For example, it would rewrite:
  (sextload:i32 $ptr)<<unindexedload>><<sextload>><<sextloadi16>
to:
  (sext:i32 (load:i16 $ptr)<<unindexedload>>)

I'd have preferred to replace the fragments and have the expansion happen
naturally as part of PatFrag expansion but the type inferencing system can't
cope with loads of types narrower than those mentioned in register classes.
This is because the SDTCisInt's on the sext constrain both the result and
operand to the 'legal' integer types (where legal is defined as 'a register
class can contain the type') which immediately rules the narrower types out.
Several targets (those with only one legal integer type) would then go on to
crash on the SDTCisOpSmallerThanOp<> when it removes all the possible types
for the result of the extend.

Also, improve isObviouslySafeToFold() slightly to automatically return true for
neighbouring instructions. There can't be any re-ordering problems if
re-ordering isn't happenning. We'll need to improve it further to handle
sign/zero-extending loads when the extend and load aren't immediate neighbours
though.

llvm-svn: 317971
2017-11-11 03:23:44 +00:00
Craig Topper
eea0adbe11 [X86] Correct the execution domain on ROUND/VROUND instructions.
llvm-svn: 317968
2017-11-11 02:26:05 +00:00
Craig Topper
ce5298b157 [X86] Remove the default for one of the arguments to some tablegen multiclasses. NFC
No one ever uses this default and probably shouldn't since it sets the execution domain to generic.

llvm-svn: 317967
2017-11-11 02:26:02 +00:00
NAKAMURA Takumi
ef658d3956 llvm/Support/TargetParser.h: Fix -fmodules build in rL317900.
llvm-svn: 317966
2017-11-11 02:05:47 +00:00
Tony Tye
c6ca5de42a [AMDGPU] Correct targets that support XNACK
Differential Revision: https://reviews.llvm.org/D39887

llvm-svn: 317955
2017-11-11 00:50:32 +00:00
Craig Topper
d70ac8094f [SelectionDAG] Make getUniformBase in SelectionDAGBuilder fail if any of the middle GEP indices are non-constant.
This is a fix for a bug in r317947. We were supposed to check that all the indices are are constant 0, but instead we're only make sure that indices that are constant are 0. Non-constant indices are being ignored.

llvm-svn: 317950
2017-11-10 23:36:56 +00:00
Zachary Turner
4103729207 Update test_debuginfo.pl script to point to new tree location.
llvm-svn: 317949
2017-11-10 23:13:14 +00:00
Craig Topper
fffdb84b35 [SelectionDAG] Teach SelectionDAGBuilder's getUniformBase for gather/scatter handling to accept GEPs with more than 2 operands if the middle operands are all 0s
Currently we can only get a uniform base from a simple GEP with 2 operands. This causes us to miss address folding opportunities for simple global array accesses as the test case shows.

This patch adds support for larger GEPs if the other indices are 0 since those don't require any additional computations to be inserted.

We may also want to handle constant splats of zero here, but I'm leaving that for future work when I have a real world example.

Differential Revision: https://reviews.llvm.org/D39911

llvm-svn: 317947
2017-11-10 22:50:50 +00:00
Evgeniy Stepanov
38b451891b [asan] Use dynamic shadow on 32-bit Android.
Summary:
The following kernel change has moved ET_DYN base to 0x4000000 on arm32:
https://marc.info/?l=linux-kernel&m=149825162606848&w=2

Switch to dynamic shadow base to avoid such conflicts in the future.

Reserve shadow memory in an ifunc resolver, but don't use it in the instrumentation
until PR35221 is fixed. This will eventually let use save one load per function.

Reviewers: kcc

Subscribers: aemerson, srhines, kubamracek, kristof.beyls, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D39393

llvm-svn: 317943
2017-11-10 22:27:48 +00:00
Martin Storsjo
89757c2b38 [llvm-cvtres] Add support for ARM64
Also change some default cases into llvm_unreachable in
WindowsResourceCOFFWriter, to make it easier to find if they
are triggerd from within e.g. lld, which supported ARM64 earlier
than llvm-cvtres did.

Differential Revision: https://reviews.llvm.org/D39892

llvm-svn: 317942
2017-11-10 22:27:41 +00:00
Mitch Phillips
2861b61472 [cfi-verify] Made FileAnalysis operate on a GraphResult rather than build one and validate it.
Refactors the behaviour of building graphs out of FileAnalysis, allowing for analysis of the GraphResult by the callee without having to rebuild the graph. Means when we want to analyse the constructed graph (planned for later revisions), we don't do repeated work.

Also makes CFI verification in FileAnalysis now return an enum that allows us to differentiate why something failed, not just that it did/didn't fail.

Reviewers: vlad.tsyrklevich

Subscribers: kcc, pcc, llvm-commits

Differential Revision: https://reviews.llvm.org/D39764

llvm-svn: 317927
2017-11-10 21:00:22 +00:00
Amaury Sechet
f3e0c5f2ce [DAGcombine] Do not replace truncate node by itself when doing constant folding, this trigger needless extra rounds of combine for nothing. NFC
llvm-svn: 317926
2017-11-10 20:59:53 +00:00
Zachary Turner
7497a5ca3a [debuginfo-tests] Make debuginfo-tests work in a standard configuration.
Previously, debuginfo-tests was expected to be checked out into
clang/test and then the tests would automatically run as part of
check-clang.  This is not a standard workflow for handling
external projects, and it brings with it some serious drawbacks
such as the inability to depend on things other than clang, which
we will need going forward.

The goal of this patch is to migrate towards a more standard
workflow.  To ease the transition for build bot maintainers,
this patch tries not to break the existing workflow, but instead
simply deprecate it to give maintainers a chance to update
the build infrastructure.

Differential Revision: https://reviews.llvm.org/D39605

llvm-svn: 317925
2017-11-10 20:57:57 +00:00
Tony Tye
8565b815bb [AMDGPU] AMDGPUUsage.rst minor corrections
Differential Revision: https://reviews.llvm.org/D39887

llvm-svn: 317924
2017-11-10 20:51:43 +00:00
Davide Italiano
012d194f43 [SimplifyCFG] Use auto * when the type is obvious. NFCI.
llvm-svn: 317923
2017-11-10 20:46:21 +00:00
Krzysztof Parzyszek
1a64d3b827 Recommit r317904: [Hexagon] Create HexagonISelDAGToDAG.h, NFC
The Windows builder did not reconstruct the HexagonGenDAGISel.inc file
after the TableGen binary has changed.

llvm-svn: 317921
2017-11-10 20:09:46 +00:00
Konstantin Zhuravlyov
17f057eda8 AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td
Differential Revision: https://reviews.llvm.org/D39880

llvm-svn: 317920
2017-11-10 20:01:58 +00:00
Daniel Neilson
2086c114aa Expand IRBuilder interface for atomic memcpy to require pointer alignments. (NFC)
Summary:
 The specification of the @llvm.memcpy.element.unordered.atomic intrinsic requires
that the pointer arguments have alignments of at least the element size. The existing
IRBuilder interface to create a call to this intrinsic does not allow for providing
the alignment of these pointer args. Having an interface that makes it easy to
construct invalid intrinsic calls doesn't seem sensible, so this patch simply
adds the requirement that one provide the argument alignments when using IRBuilder
to create atomic memcpy calls.

llvm-svn: 317918
2017-11-10 19:38:12 +00:00
Krzysztof Parzyszek
66b30dd685 Revert "[Hexagon] Create HexagonISelDAGToDAG.h, NFC"
This reverts r317904: broke Windows build.

llvm-svn: 317916
2017-11-10 19:27:18 +00:00
Craig Topper
1ab15f68c8 [X86] Merge the template method selectAddrOfGatherScatterNode into selectVectorAddr. NFCI
Just need to initialize a couple variables differently based on the node type. No need for a whole separate template method.

llvm-svn: 317915
2017-11-10 19:26:04 +00:00
Adrian Prantl
4d354738de Add back target triple to test which I accidentally removed.
llvm-svn: 317912
2017-11-10 19:22:02 +00:00
Sanjoy Das
eb77be5924 [CVP] Remove some {s|u}add.with.overflow checks.
Summary:
This adds logic to CVP to remove some overflow checks.  It uses LVI to remove
operations with at least one constant.  Specifically, this can remove many
overflow intrinsics immediately following an overflow check in the source code,
such as:

if (x < INT_MAX)
    ... x + 1 ...

Patch by Joel Galenson!

Reviewers: sanjoy, regehr

Reviewed By: sanjoy

Subscribers: fhahn, pirama, srhines, llvm-commits

Differential Revision: https://reviews.llvm.org/D39483

llvm-svn: 317911
2017-11-10 19:13:35 +00:00
Mandeep Singh Grang
f387fa649a [RISCV] Silence an unused variable warning in release builds [NFC]
Summary:
Also minor cleanups:
1. Avoided multiple calls to Fixup.getKind()
2. Avoided multiple calls to getFixupKindInfo()
3. Removed a redundant return.

Reviewers: asb, apazos

Reviewed By: asb

Subscribers: rbar, johnrusso, llvm-commits

Differential Revision: https://reviews.llvm.org/D39881

llvm-svn: 317908
2017-11-10 19:09:28 +00:00
Craig Topper
382ee62e1f [X86] Add test case to demonstrate failure to fold the address computation of a simple gather from a global array. NFC
llvm-svn: 317905
2017-11-10 18:48:18 +00:00
Krzysztof Parzyszek
fd31de271f [Hexagon] Create HexagonISelDAGToDAG.h, NFC
llvm-svn: 317904
2017-11-10 18:39:45 +00:00
Krzysztof Parzyszek
a38d7036dc Allow separation of declarations and definitions in <Target>ISelDAGToDAG.inc
This patch adds the ability to include the member function declarations
in the instruction selector class separately from the member bodies.

Defining GET_DAGISEL_DECL macro to any value will only include the member
declarations. To include bodies, define GET_DAGISEL_BODY macro to be the
selector class name. Example:

  class FooDAGToDAGISel : public SelectionDAGISel {
    // Pull in declarations only.
    #define GET_DAGISEL_DECL
    #include "FooISelDAGToDAG.inc"
  };

  // Include the function bodies (with names qualified with the provided
  // class name).
  #define GET_DAGISEL_BODY FooDAGToDAGISel
  #include "FooISelDAGToDAG.inc"

When neither of the two macros are defined, the function bodies are emitted
inline (in the same way as before this patch).

Differential Revision: https://reviews.llvm.org/D39596

llvm-svn: 317903
2017-11-10 18:36:04 +00:00
Lang Hames
f8fa757956 [ADT] Rewrite mapped_iterator in terms of iterator_adaptor_base.
Summary:
This eliminates the boilerplate implementation of the iterator interface in
mapped_iterator.

This patch also adds unit tests that verify that the mapped function is applied
by operator* and operator->, and that references returned by the map function
are returned via operator*.

Reviewers: dblaikie, chandlerc

Subscribers: llvm-commits, mgorny

Differential Revision: https://reviews.llvm.org/D39855

llvm-svn: 317902
2017-11-10 17:41:28 +00:00
Craig Topper
f3eb90626c [X86] Add a def file to CPU vendor, type, and subtype encodings used by Host.cpp
Summary:
I want to leverage this to clean up some of the code in clang. This will allow us to simplify D39521 which was trying to do some of the same.

If we accurately keep the code in Host.cpp synced with new CPUs added to compile-rt/libgcc we should be able to use this file as a proxy for what's implemented in the libraries.

The entries for the CPUs recognized by the libraries use separate macros that define additional parameters like the name for __builtin_cpu_is and an alias string for the couple cases where __builtin_cpu_is accepts two different names.

All of the macros contain an ARCHNAME that is usually the same as the __builtin_cpu_is string, but sometimes isn't. This represents the name recognized by X86.td and -march.

I'm following the precedent set by ARM and AArch64 and adding this information to lib/Support/TargetParser.cpp

Reviewers: erichkeane, echristo, asbirlea

Reviewed By: echristo

Subscribers: llvm-commits, aemerson, kristof.beyls

Differential Revision: https://reviews.llvm.org/D39782

llvm-svn: 317900
2017-11-10 17:10:57 +00:00
Bob Haarman
50bb177930 LTO: don't fatal when value for cache key already exists
Summary:
LTO/Caching.cpp uses file rename to atomically set the value for a
cache key. On Windows, this fails when the destination file already
exists. Previously, LLVM would report_fatal_error in such
cases. However, because the old and the new value for the cache key
are supposed to be equivalent, it actually doesn't matter which one we
keep. This change makes it so that failing the rename when an openable
file with the desired name already exists causes us to report success
instead of fataling.

Reviewers: pcc, hans

Subscribers: mehdi_amini, llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D39874

llvm-svn: 317899
2017-11-10 17:08:21 +00:00
Adrian Prantl
cb6f1db18e Move test into X86 subdirectory.
llvm-svn: 317896
2017-11-10 16:36:04 +00:00
Jatin Bhateja
8e6a1223b6 [WebAssembly] Fix stack offsets of return values from call lowering.
Summary: Fixes PR35220

Reviewers: vadimcn, alexcrichton

Reviewed By: alexcrichton

Subscribers: pepyakin, alexcrichton, jfb, dschuff, sbc100, jgravelle-google, llvm-commits, aheejin

Differential Revision: https://reviews.llvm.org/D39866

llvm-svn: 317895
2017-11-10 16:26:04 +00:00