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Author SHA1 Message Date
Renato Golin
fa6e1c461b [ARM] Support and tests for transform of LDR rt, = to MOV
This change implements the transformation in processInstruction() for the
LDR rt, =expression to MOV rt, expression when the expression can be evaluated
and can fit into the immediate field of the MOV or a MVN.

Across the ARM and Thumb instruction sets there are several cases to consider,
each with a different range of representatble constants.

In ARM we have:
 * Modified immediate (All ARM architectures)
 * MOVW (v6t2 and above)

In Thumb we have:
 * Modified immediate (v6t2, v7m and v8m.mainline)
 * MOVW (v6t2, v7m, v8.mainline and v8m.baseline)
 * Narrow Thumb MOV that can be used in an IT block (non flag-setting)

If the immediate fits any of the available alternatives then we make the transformation.

Fixes 25722.

Patch by Peter Smith.

llvm-svn: 269354
2016-05-12 21:22:42 +00:00
Renato Golin
fd950d2ff0 [ARM] Fixup tests to take into account mov translation. NFC.
Alter instances in the test-suite that use immediates that can be represented
in the immediate field of a MOV. The reason for doing this is that when the
LDR rt,=imm transformation to MOV rt, imm the existing tests do not need to
be modified.

Required by the patch that fixes PR25722.

Patch by Peter Smith.

llvm-svn: 269353
2016-05-12 21:22:37 +00:00
Dan Gohman
39414df67d Followup to 258750; update all MC tests to use .p2align .
llvm-svn: 258754
2016-01-26 00:27:59 +00:00
David Peixotto
569d73691e MC: support different sized constants in constant pools
On AArch64 the pseudo instruction ldr <reg>, =... supports both
32-bit and 64-bit constants. Add support for 64 bit constants for
the pools to support the pseudo instruction fully.

Changes the AArch64 ldr-pseudo tests to use 32-bit registers and
adds tests with 64-bit registers.

Patch by Janne Grunau!

Differential Revision: http://reviews.llvm.org/D4279

llvm-svn: 213387
2014-07-18 16:05:14 +00:00
David Peixotto
a66e68bb52 Implement the ldr-pseudo opcode for ARM assembly
The ldr-pseudo opcode is a convenience for loading 32-bit constants.
It is converted into a pc-relative load from a constant pool. For
example,

  ldr r0, =0x10001
  ldr r1, =bar

will generate this output in the final assembly

  ldr r0, .Ltmp0
  ldr r1, .Ltmp1
  ...
  .Ltmp0: .long 0x10001
  .Ltmp1: .long bar

Sketch of the LDR pseudo implementation:
  Keep a map from Section => ConstantPool

  When parsing ldr r0, =val
    parse val as an MCExpr
    get ConstantPool for current Section
    Label = CreateTempSymbol()
    remember val in ConstantPool at next free slot
    add operand to ldr that is MCSymbolRef of Label

  On finishParse() callback
    Write out all non-empty constant pools
    for each Entry in ConstantPool
      Emit Entry.Label
      Emit Entry.Value

Possible improvements to be added in a later patch:
  1. Does not convert load of small constants to mov
     (e.g. ldr r0, =0x1 => mov r0, 0x1)
  2. Does reuse constant pool entries for same constant

The implementation was tested for ARM, Thumb1, and Thumb2 targets on
linux and darwin.

llvm-svn: 197708
2013-12-19 18:12:36 +00:00