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1831 Commits

Author SHA1 Message Date
Jim Grosbach
f3d495fbbd ARM NEON "vmov.i8" immediate assembly parsing and encoding. 
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.

llvm-svn: 142293
 2011-10-17 22:26:03 +00:00
Craig Topper
6c900d9810 Add X86 PEXTR and PDEP instructions. 
llvm-svn: 142141
 2011-10-16 16:50:08 +00:00
Craig Topper
2cd868184c Add X86 BZHI instruction as well as BMI2 feature detection. 
llvm-svn: 142122
 2011-10-16 07:55:05 +00:00
Craig Topper
91b4292682 Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. 
llvm-svn: 142117
 2011-10-16 07:05:40 +00:00
Chris Lattner
321335142c Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance 
the X86 asmparser to produce ranges in the one case that was annoying me, for example:

test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
              ^~~~~~~

It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use 
ranges where appropriate if someone is interested.

llvm-svn: 142106
 2011-10-16 04:47:35 +00:00
Craig Topper
4c6357d4af Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen 
llvm-svn: 142105
 2011-10-16 03:51:13 +00:00
Craig Topper
62e63d9bb9 Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. 
llvm-svn: 142082
 2011-10-15 20:46:47 +00:00
Owen Anderson
96976108b1 Update test for disabling of code/data marker labels in ELF. 
llvm-svn: 142003
 2011-10-14 21:12:55 +00:00
Craig Topper
0a11eb1b21 Add X86 ANDN instruction. Including instruction selection. 
llvm-svn: 141947
 2011-10-14 07:06:56 +00:00
Craig Topper
6b2120a8e1 Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. 
llvm-svn: 141939
 2011-10-14 03:21:46 +00:00
Bill Wendling
2a571af745 Revert r141854 because it was causing failures: 
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101

--- Reverse-merging r141854 into '.':
U    test/MC/Disassembler/X86/x86-32.txt
U    test/MC/Disassembler/X86/simple-tests.txt
D    test/CodeGen/X86/bmi.ll
U    lib/Target/X86/X86InstrInfo.td
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86.td
U    lib/Target/X86/X86Subtarget.h

llvm-svn: 141857
 2011-10-13 07:48:07 +00:00
Craig Topper
eb29e18c9b Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. 
llvm-svn: 141854
 2011-10-13 07:09:14 +00:00
Kevin Enderby
974c799a5a Finish supporting cpp #file/line comments in assembler for error messages. So 
for cpp pre-processed assembly we give correct filename and line numbers when
reporting errors in assembly files when using clang and -integrated-as on .s
files. rdar://8998895

llvm-svn: 141814
 2011-10-12 21:38:39 +00:00
Jim Grosbach
422576b6e8 Thumb2 assembly parsing and encoding for LDC/STC. 
llvm-svn: 141811
 2011-10-12 20:54:17 +00:00
Jim Grosbach
2a501996ab ARM encoding tests for STC. 
llvm-svn: 141787
 2011-10-12 17:36:13 +00:00
Jim Grosbach
eb7acc978a ARM parsing and encoding for the <option> form of LDC/STC instructions. 
llvm-svn: 141786
 2011-10-12 17:34:41 +00:00
Jim Grosbach
d2cfc2b31f ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. 
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.

llvm-svn: 141721
 2011-10-11 21:55:36 +00:00
Jim Grosbach
313a74d565 Update test for r141704. 
llvm-svn: 141705
 2011-10-11 20:18:50 +00:00
Nick Lewycky
6bd023fab9 Apparently, sometimes llvm-nm doesn't put the undefined symbol at the top. Take 
that into account and test for no U's showing up in the middle, which is what
we really wanted to test for.

llvm-svn: 141653
 2011-10-11 06:58:11 +00:00
Craig Topper
c498c5c0e6 Add X86 LZCNT instruction. Including instruction selection support. 
llvm-svn: 141651
 2011-10-11 06:44:02 +00:00
Craig Topper
7ae42fbd7e Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. 
llvm-svn: 141642
 2011-10-11 04:34:23 +00:00
Nick Lewycky
509687695f Also create a shndx even if there are no symbols. This lets us test 
.symtab_shndx reading and writing together, and finally we have a testcase for
r141440.

llvm-svn: 141641
 2011-10-11 03:54:50 +00:00
Jakob Stoklund Olesen
f46c756068 Insert dummy ED table entries for pseudo-instructions. 
The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.

Add a test case for xorps which has a very high opcode that exposes this
problem.

llvm-svn: 141562
 2011-10-10 18:30:16 +00:00
Craig Topper
9b7ab95570 Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. 
llvm-svn: 141505
 2011-10-09 07:31:39 +00:00
Jim Grosbach
6322a90e2d Enable ARM mode VDUP(scalar) tests. 
llvm-svn: 141447
 2011-10-07 23:57:03 +00:00
Jim Grosbach
94980a23e6 ARM NEON assembly parsing and encoding for VDUP(scalar). 
llvm-svn: 141446
 2011-10-07 23:56:00 +00:00
Craig Topper
761bf0e7d3 Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE. 
llvm-svn: 141358
 2011-10-07 07:02:24 +00:00
Craig Topper
71e09ffe7b Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT. 
llvm-svn: 141354
 2011-10-07 05:53:50 +00:00
Craig Topper
f083691b6d Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. 
llvm-svn: 141353
 2011-10-07 05:35:38 +00:00
Jim Grosbach
53b2b56db8 Tidy up tests. Un-XFAIL file and mark individual tests as FIXME instead. 
llvm-svn: 141321
 2011-10-06 22:04:05 +00:00
Jim Grosbach
ec12700fe4 Fix and clean up tests. Un-XFAIL. 
llvm-svn: 141318
 2011-10-06 21:32:50 +00:00
Jim Grosbach
17ae6aae38 Fix and clean up tests. Un-XFAIL. 
llvm-svn: 141316
 2011-10-06 21:28:30 +00:00
Craig Topper
2614f6f120 Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. 
llvm-svn: 141274
 2011-10-06 06:44:41 +00:00
Owen Anderson
2d1e930b65 Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set. 
llvm-svn: 141190
 2011-10-05 17:16:40 +00:00
Owen Anderson
e255773f3d Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment. 
llvm-svn: 141135
 2011-10-04 23:26:17 +00:00
Jim Grosbach
386f7cb041 Tidy up formatting. 
llvm-svn: 141123
 2011-10-04 21:43:51 +00:00
Jim Grosbach
f3373734b4 Un-XFAIL file. Comment out individual failing instructions. 
llvm-svn: 141117
 2011-10-04 21:16:42 +00:00
Jim Grosbach
6f00406f92 Tidy up formatting. 
llvm-svn: 141115
 2011-10-04 20:52:57 +00:00
Jim Grosbach
0db58d15e6 Un-XFAIL file. Fix incorrect CHECK lines. General format cleanup. 
llvm-svn: 141114
 2011-10-04 20:50:05 +00:00
Jim Grosbach
3df5c47ec8 Un-XFAIL file. Fix incorrect CHECK line. General format cleanup. 
llvm-svn: 141113
 2011-10-04 20:46:49 +00:00
Jim Grosbach
4770714494 Tidy up formatting. 
llvm-svn: 141111
 2011-10-04 20:42:35 +00:00
Jim Grosbach
dee6bd4517 Un-XFAIL file. Fix incorrect CHECK line. 
llvm-svn: 141110
 2011-10-04 20:42:09 +00:00
Jim Grosbach
d7449dd23f Un-XFAIL the file. Disable only the individual tests that aren't working yet. 
llvm-svn: 141108
 2011-10-04 20:34:11 +00:00
Jim Grosbach
58f067b61b Un-XFAIL the file. Disable only the individual tests that aren't working yet. 
llvm-svn: 141099
 2011-10-04 18:43:15 +00:00
Jim Grosbach
93ad98accb Tidy up. Formatting. 
llvm-svn: 141096
 2011-10-04 17:49:45 +00:00
Craig Topper
9d32602cfd Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. 
llvm-svn: 141065
 2011-10-04 06:30:42 +00:00
Jim Grosbach
8170db143e Tidy up. These tests are covered in the .s file tests now. 
llvm-svn: 141047
 2011-10-03 23:40:13 +00:00
Jim Grosbach
f38874e79e ARM assembly parsing and encoding for VMOV immediate. 
llvm-svn: 141046
 2011-10-03 23:38:36 +00:00
Jim Grosbach
c69258c747 ARM parsing/encoding for VCMP/VCMPE. 
llvm-svn: 141038
 2011-10-03 22:30:24 +00:00
Jim Grosbach
21a9f8f50f ARM assembly parsing and encoding for VMRS/FMSTAT. 
llvm-svn: 141025
 2011-10-03 21:12:43 +00:00
Jim Grosbach
0e385170ee Update test for 141010. 
llvm-svn: 141022
 2011-10-03 20:58:08 +00:00
Jim Grosbach
1651804363 Tidy up a bit. Formatting. 
llvm-svn: 141010
 2011-10-03 17:59:31 +00:00
Craig Topper
df04bee9b2 Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. 
llvm-svn: 141007
 2011-10-03 17:28:23 +00:00
Craig Topper
4456c94f70 Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode. 
llvm-svn: 140997
 2011-10-03 08:14:29 +00:00
Craig Topper
a3372bd949 Test updates that were supposed to go with r140993. 
llvm-svn: 140994
 2011-10-03 07:53:59 +00:00
Craig Topper
f776e3b410 Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. 
llvm-svn: 140974
 2011-10-02 21:08:12 +00:00
Craig Topper
5c8feca34f Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344. 
llvm-svn: 140971
 2011-10-02 16:56:09 +00:00
Craig Topper
43fd621df8 Fix disassembling of INVEPT and INVVPID to take operands 
llvm-svn: 140955
 2011-10-01 21:20:14 +00:00
Craig Topper
99ad3cc23e Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. 
llvm-svn: 140954
 2011-10-01 19:54:56 +00:00
James Molloy
c4fcff419c Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. 
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.

llvm-svn: 140696
 2011-09-28 14:21:38 +00:00
Jim Grosbach
b503a2183e ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w. 
Add inst alias to handle these assembly forms. Add tests, too.

rdar://10178799

llvm-svn: 140647
 2011-09-27 22:18:54 +00:00
Owen Anderson
bfb83aae27 Fix an incorrect decoder test. 
llvm-svn: 140579
 2011-09-26 23:08:34 +00:00
Owen Anderson
c811b1bed2 Remove incorrect testcases. 
llvm-svn: 140572
 2011-09-26 22:13:55 +00:00
Craig Topper
a08173e534 Fix VEX decoding in i386 mode. Fixes PR11008. 
llvm-svn: 140515
 2011-09-26 05:12:43 +00:00
Owen Anderson
fc9a0d104c Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0. 
llvm-svn: 140426
 2011-09-23 22:25:02 +00:00
Owen Anderson
f9ff097fdd Fix incorrect disassembly test. 
llvm-svn: 140423
 2011-09-23 22:05:54 +00:00
Owen Anderson
53c6b08ad8 Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions. 
llvm-svn: 140420
 2011-09-23 21:26:40 +00:00
Owen Anderson
071eb7580a Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated. 
llvm-svn: 140415
 2011-09-23 21:07:25 +00:00
Craig Topper
655f8a01e6 Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700. 
llvm-svn: 140370
 2011-09-23 06:57:25 +00:00
Craig Topper
95f048d1ff Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960 
llvm-svn: 140299
 2011-09-22 07:01:50 +00:00
Owen Anderson
22ab29756b Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused. 
llvm-svn: 140284
 2011-09-21 23:53:44 +00:00
Owen Anderson
7b134fe54c Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123. 
llvm-svn: 140283
 2011-09-21 23:44:46 +00:00
Bruno Cardoso Lopes
906f64c461 The wrong relocation was being emitted for several SSSE3 instructions. 
This fixes PR10963. Thanks to Benjamin for finding the wrong tablegen
declaration.

llvm-svn: 140184
 2011-09-20 21:39:21 +00:00
Owen Anderson
4177cfc809 Port over more Thumb2 encoding tests to decoding tests. 
llvm-svn: 140152
 2011-09-20 17:44:48 +00:00
Jim Grosbach
dd8f345dc3 Nuke obsolete test file. 
llvm-svn: 140127
 2011-09-20 01:03:51 +00:00
Jim Grosbach
169f556004 Thumb2 assembly parsing and encoding for WFE/WFI/YIELD. 
llvm-svn: 140126
 2011-09-20 00:48:56 +00:00
Jim Grosbach
e936bdc286 Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH. 
llvm-svn: 140125
 2011-09-20 00:46:54 +00:00
Jim Grosbach
79dac4bf28 Thumb2 assembly parsing and encoding for USUB8/USUB16. 
llvm-svn: 140120
 2011-09-20 00:31:57 +00:00
Jim Grosbach
5ca3bddd26 Thumb2 assembly parsing and encoding for USAX. 
llvm-svn: 140119
 2011-09-20 00:30:45 +00:00
Jim Grosbach
f6d79c7c40 Thumb2 assembly parsing and encoding for USAT16. 
llvm-svn: 140118
 2011-09-20 00:28:25 +00:00
Jim Grosbach
4768b6b0d4 Thumb2 assembly parsing and encoding for USAT. 
llvm-svn: 140117
 2011-09-20 00:27:36 +00:00
Jim Grosbach
d9a8af05ea Tidy up. 
llvm-svn: 140114
 2011-09-20 00:24:37 +00:00
Jim Grosbach
c67e9e9885 Thumb2 assembly parsing and encoding for UQSAD8/USADA8. 
llvm-svn: 140113
 2011-09-20 00:23:51 +00:00
Jim Grosbach
0b329532eb Thumb2 assembly parsing and encoding for UQSUB16/UQSUB8. 
llvm-svn: 140112
 2011-09-20 00:20:44 +00:00
Jim Grosbach
18a65f1fe6 Thumb2 assembly parsing and encoding for UQASX/UQSAX. 
llvm-svn: 140111
 2011-09-20 00:18:52 +00:00
Jim Grosbach
f5f3242925 Thumb2 assembly parsing and encoding for UQADD16/UQADD8. 
llvm-svn: 140110
 2011-09-20 00:15:03 +00:00
Bruno Cardoso Lopes
de0dc10d6d Fix PR10949. Fix the encoding of VMOVPQIto64rr. 
llvm-svn: 140098
 2011-09-19 23:36:59 +00:00
Jim Grosbach
d4a347b1e8 Tidy up a bit. 
llvm-svn: 140096
 2011-09-19 23:34:18 +00:00
Jim Grosbach
2341e082fc Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL. 
llvm-svn: 140095
 2011-09-19 23:31:02 +00:00
Jim Grosbach
3a7a6c8acf Thumb2 assembly parsing and encoding for UHSUB16/UHSUB8. 
llvm-svn: 140089
 2011-09-19 23:15:36 +00:00
Jim Grosbach
dd8d66f3aa Thumb2 assembly parsing and encoding for UHASX/UHSAX. 
llvm-svn: 140088
 2011-09-19 23:13:25 +00:00
Jim Grosbach
0bec90ffe5 Thumb2 assembly parsing and encoding for UHADD16/UHADD8. 
llvm-svn: 140087
 2011-09-19 23:08:24 +00:00
Jim Grosbach
ec1bd1e213 Thumb2 assembly parsing and encoding for UBFX. 
llvm-svn: 140086
 2011-09-19 23:06:38 +00:00
Jim Grosbach
a5a28c45e5 Thumb2 assembly parsing and encoding for UASX. 
llvm-svn: 140085
 2011-09-19 23:05:22 +00:00
Jim Grosbach
4d8d362374 Fix copy/past-o. Gotta remember that 'modify' step... 
llvm-svn: 140082
 2011-09-19 22:53:00 +00:00
Jim Grosbach
2ef3c31987 Thumb2 assembly parsing and encoding for UADD16/UADD8. 
llvm-svn: 140081
 2011-09-19 22:52:27 +00:00
Jim Grosbach
7941ca00ab Thumb2 assembly parsing and encoding for TST. 
llvm-svn: 140080
 2011-09-19 22:46:06 +00:00
Jim Grosbach
6da9e6b23d Thumb2 assembly parsing and encoding for TBB/TBH. 
llvm-svn: 140078
 2011-09-19 22:21:13 +00:00
Jim Grosbach
2185babd50 Thumb2 assembly parsing and encoding for TEQ. 
llvm-svn: 140070
 2011-09-19 21:41:21 +00:00
Jim Grosbach
6e092f297b Remove FIXME. TBB/TBH are Thumb mode only instructions. 
llvm-svn: 140048
 2011-09-19 20:30:29 +00:00
Jim Grosbach
c7fa5f0c00 Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH. 
llvm-svn: 140047
 2011-09-19 20:29:33 +00:00
Owen Anderson
b843f3625d Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests. 
llvm-svn: 140032
 2011-09-19 18:07:10 +00:00
Jim Grosbach
c677995374 Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH. 
llvm-svn: 140029
 2011-09-19 17:56:37 +00:00
Jim Grosbach
06677b6b4c Thumb2 assembly parsing and encoding for SVC. 
llvm-svn: 140025
 2011-09-19 17:40:35 +00:00
Jim Grosbach
a5bdf3b221 Thumb2 assembly parsing and encoding for SUB(register). 
llvm-svn: 140024
 2011-09-19 17:37:48 +00:00
Stepan Dyatkovskiy
b769edad5b Added regression test for bug #10869. 
llvm-svn: 140012
 2011-09-19 07:48:08 +00:00
Owen Anderson
df512e9961 Add a testcase for another corner-case decoding. 
llvm-svn: 139970
 2011-09-16 23:15:29 +00:00
Jim Grosbach
95242bff08 Thumb2 assembly parsing and encoding for SUB(immediate). 
llvm-svn: 139966
 2011-09-16 22:58:42 +00:00
Owen Anderson
eae0eee720 Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32). 
llvm-svn: 139964
 2011-09-16 22:29:48 +00:00
Jim Grosbach
3a58f722bf Thumb2 assembly parsing and encoding for STRT. 
llvm-svn: 139963
 2011-09-16 22:27:12 +00:00
Jim Grosbach
41ece87fae Thumb2 assembly parsing and encoding for LDRHT/STRHT. 
llvm-svn: 139962
 2011-09-16 22:26:01 +00:00
Jim Grosbach
e9f1da5dec Thumb2 assembly parsing and encoding for STREX/STREXB/STREXH/STREXD. 
llvm-svn: 139961
 2011-09-16 22:22:07 +00:00
Jim Grosbach
f8313f60b3 Thumb2 assembly parsing and encoding for STRD. 
llvm-svn: 139960
 2011-09-16 22:19:38 +00:00
Jim Grosbach
d0ef17692a Simplify comment. There's no Thumb LDRD(register) encoding. That's ARM only. 
llvm-svn: 139959
 2011-09-16 22:18:42 +00:00
Owen Anderson
3a487c8c9b Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's. 
llvm-svn: 139958
 2011-09-16 22:17:02 +00:00
Jim Grosbach
c3834c5da5 Thumb2 assembly parsing and encoding for STRBT. 
llvm-svn: 139957
 2011-09-16 22:15:51 +00:00
Jim Grosbach
3caa04dc32 Thumb2 assembly parsing and encoding for STRH. 
llvm-svn: 139956
 2011-09-16 22:12:19 +00:00
Jim Grosbach
771b6c5fe3 Remove test of undocumented format. 
llvm-svn: 139955
 2011-09-16 22:09:58 +00:00
Jim Grosbach
b181e68ab6 Thumb2 assembly parsing and encoding for STRB. 
llvm-svn: 139954
 2011-09-16 22:09:19 +00:00
Jim Grosbach
f75d317df4 Shuffle a few more thumb2 tests to match the comment headings. 
llvm-svn: 139952
 2011-09-16 22:01:18 +00:00
Jim Grosbach
bc84a55ed8 Thumb2 tests for STR(literal), STR(register) and STR pre/post indexed immediate. 
llvm-svn: 139951
 2011-09-16 21:59:13 +00:00
Jim Grosbach
c9eb37a7c9 Shuffle a few tests around. 
llvm-svn: 139950
 2011-09-16 21:57:10 +00:00
Owen Anderson
5804085f26 Fix disassembly of Thumb2 LDRSH with a #-0 offset. 
llvm-svn: 139943
 2011-09-16 21:08:33 +00:00
Jim Grosbach
916a6c71aa Thumb2 assembly parsing and encoding for STR(immediate). 
Add aliases for STRB/STRH while there. Tests forthcoming for those.

llvm-svn: 139942
 2011-09-16 21:06:12 +00:00
Jim Grosbach
03c39637ee Thumb2 assembly parsing and encoding for STMDB. 
llvm-svn: 139940
 2011-09-16 20:58:38 +00:00
Jim Grosbach
13af7198d5 Thumb2 assembly parsing and encoding for STMIA. 
llvm-svn: 139938
 2011-09-16 20:50:13 +00:00
Jim Grosbach
0c71c46758 Thumb2 assembly parsing and encoding for SSUB16/SSUB8. 
llvm-svn: 139931
 2011-09-16 18:52:36 +00:00
Jim Grosbach
47ff106753 Thumb2 assembly parsing and encoding for SSAX. 
llvm-svn: 139929
 2011-09-16 18:37:10 +00:00
Jim Grosbach
eb47e416c2 Thumb2 assembly parsing and encoding for SSAT16. 
llvm-svn: 139927
 2011-09-16 18:33:22 +00:00
Jim Grosbach
6f6453f64b Thumb2 assembly parsing and encoding for SSAT. 
llvm-svn: 139926
 2011-09-16 18:32:30 +00:00
Jim Grosbach
5a8b63fe51 Thumb2 assembly parsing and encoding for SRS. 
llvm-svn: 139925
 2011-09-16 18:25:22 +00:00
Jim Grosbach
3cac04dd75 Thumb2 assembly parsing and encoding for SMMUSD/SMUSDX. 
llvm-svn: 139923
 2011-09-16 18:08:48 +00:00
Jim Grosbach
b8b9febaa7 Thumb2 assembly parsing and encoding for SMMULWB/SMULWT. 
llvm-svn: 139922
 2011-09-16 18:07:18 +00:00
Jim Grosbach
0f1615c381 Thumb2 assembly parsing and encoding for SMMULL. 
llvm-svn: 139921
 2011-09-16 18:05:48 +00:00
Jim Grosbach
4c944a22e2 Fix comment. 
llvm-svn: 139919
 2011-09-16 18:03:00 +00:00
Jim Grosbach
f39a3fcb4f Thumb2 assembly parsing and encoding for SMULBB/SMULBT/SMULTB/SMULTT. 
llvm-svn: 139918
 2011-09-16 18:02:36 +00:00
Jim Grosbach
0066bd4289 Thumb2 assembly parsing and encoding for SMMUAD'dib. 
llvm-svn: 139917
 2011-09-16 17:58:21 +00:00
Jim Grosbach
89777cb2f9 Thumb2 assembly parsing and encoding for SMMUL/SMMULR. 
llvm-svn: 139916
 2011-09-16 17:56:06 +00:00
Owen Anderson
ceb2fb9548 Port over more Thumb2 assembly tests to disassembly tests. 
llvm-svn: 139915
 2011-09-16 17:56:04 +00:00
Owen Anderson
8bc7120609 Port over more Thumb2 assembly tests to disassembly tests. 
llvm-svn: 139912
 2011-09-16 17:22:48 +00:00
Jim Grosbach
fa3986ddbe Thumb2 assembly parsing and encoding for SMMLS/SMMLSR. 
llvm-svn: 139911
 2011-09-16 17:16:55 +00:00
Jim Grosbach
25e57a3e7a Thumb2 assembly parsing and encoding for SMMLA/SMMLAR. 
llvm-svn: 139910
 2011-09-16 17:15:18 +00:00
Jim Grosbach
3c3a9393ab Thumb2 assembly parsing and encoding for SMLSLD/SMLSLDX. 
llvm-svn: 139909
 2011-09-16 17:10:44 +00:00
Jim Grosbach
5d7af41c05 Thumb2 assembly parsing and encoding for SMLSD/SMLSDX. 
llvm-svn: 139908
 2011-09-16 17:08:45 +00:00
Jim Grosbach
599dd49609 Thumb2 assembly parsing and encoding for SMLAWB/SMLAWT. 
llvm-svn: 139907
 2011-09-16 17:03:01 +00:00
Jim Grosbach
9e471afd9c Thumb2 assembly parsing and encoding for SMLALD/SMLALDX. 
llvm-svn: 139906
 2011-09-16 16:58:03 +00:00
Jim Grosbach
77ece5c9a0 Thumb2 assembly parsing and encoding for SMLALBB/SMLALBT/SMLALTB/SMLALTT. 
llvm-svn: 139905
 2011-09-16 16:53:25 +00:00
Jim Grosbach
d382581509 Thumb2 assembly parsing and encoding for SMLAL. 
llvm-svn: 139902
 2011-09-16 16:38:00 +00:00
Jim Grosbach
5147a59e59 Thumb2 assembly parsing and encoding for SMLAD/SMLADX. 
llvm-svn: 139884
 2011-09-16 00:09:37 +00:00
Jim Grosbach
9fb6f7e9fc Thumb2 assembly parsing and encoding for SMLABB/SMLABT/SMLATB/SMLATT. 
llvm-svn: 139881
 2011-09-16 00:00:23 +00:00