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Commit Graph

162865 Commits

Author SHA1 Message Date
Tony Tye
b07aa1c281 [AMDGPU] Add gfx902 product names
Differential Revision: https://reviews.llvm.org/D45609

llvm-svn: 330081
2018-04-14 01:58:10 +00:00
Heejin Ahn
c7412ff5cb [WebAssembly] Fix a bug in MachineBasicBlock::findDebugLoc() call
Summary:
InsertPos is within the bacic block `Header`, so `findDebugLoc()` should
be called on not `MBB` but `Header` instead.

Reviewers: yurydelendik

Subscribers: jfb, dschuff, aprantl, sbc100, jgravelle-google, sunfish, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D45648

llvm-svn: 330079
2018-04-14 00:12:12 +00:00
Craig Topper
0441629838 [X86] Add the bizarro movsww and movzww mnemonics for the disassembler.
The destination size of the movzx/movsx instruction is controlled by the normal operand size mechanisms. Only the input type is fixed.

This means that a 0x66 prefix on the encoding for zext/sext 16->32 should really produce a 16->16 instruction. Functionally this is equivalent to a GR16->GR16 move since bits 16 and above will be preserved. So nothing is actually extended.

llvm-svn: 330078
2018-04-13 23:57:54 +00:00
Tim Northover
ab39f1740c MachO: trap unreachable instructions
Debugability is more important than saving 4 bytes to let us to fall
through to nonense.

llvm-svn: 330073
2018-04-13 22:25:20 +00:00
Roman Lebedev
319405d79c [InstCombine][NFC] masked-merge: add 'and' tests, too.
(and plain 'or', for completeness sake.)

After submitting D45631, i have realized that it will *already*
affect 'and' pattern, and it was obvious that there were no
good test patterns to show that.

Since the masked-merge.ll is getting kinda big,
unify naming schemes a bit, and split into 'xor'/'and'/'or'
testfiles, with the only difference being the last operation.

llvm-svn: 330072
2018-04-13 21:57:01 +00:00
Roman Tereshin
d348c8a97b [DebugInfo][OPT] NFC follow-up on "Fixing a couple of DI duplication bugs of CloneModule"
llvm-svn: 330070
2018-04-13 21:23:11 +00:00
Roman Tereshin
eecdf22144 [DebugInfo][OPT] Fixing a couple of DI duplication bugs of CloneModule
As demonstrated by the regression tests added in this patch, the
following cases are valid cases:

1. A Function with no DISubprogram attached, but various debug info
  related to its instructions, coming, for instance, from an inlined
  function, also defined somewhere else in the same module;
2. ... or coming exclusively from the functions inlined and eliminated
  from the module entirely.

The ValueMap shared between CloneFunctionInto calls within CloneModule
needs to contain identity mappings for all of the DISubprogram's to
prevent them from being duplicated by MapMetadata / RemapInstruction
calls, this is achieved via DebugInfoFinder collecting all the
DISubprogram's. However, CloneFunctionInto was missing calls into
DebugInfoFinder for functions w/o DISubprogram's attached, but still
referring DISubprogram's from within (case 1). This patch fixes that.

The fix above, however, exposes another issue: if a module contains a
DISubprogram referenced only indirectly from other debug info
metadata, but not attached to any Function defined within the module
(case 2), cloning such a module causes a DICompileUnit duplication: it
will be moved in indirecty via a DISubprogram by DebugInfoFinder first
(because of the first bug fix described above), without being
self-mapped within the shared ValueMap, and then will be copied during
named metadata cloning. So this patch makes sure DebugInfoFinder
visits DICompileUnit's referenced from DISubprogram's as it goes w/o
re-processing llvm.dbg.cu list over and over again for every function
cloned, and makes sure that CloneFunctionInto self-maps
DICompileUnit's referenced from the entire function, not just its own
DISubprogram attached that may also be missing.

The most convenient way of tesing CloneModule I found is to rely on
CloneModule call from `opt -run-twice`, instead of writing tedious
unit tests. That feature has a couple of properties that makes it hard
to use for this purpose though:

1. CloneModule doesn't copy source filename, making `opt -run-twice`
  report it as a difference.
2. `opt -run-twice` does the second run on the original module, not
  its clone, making the result of cloning completely invisible in opt's
  actual output with and without `-run-twice` both, which directly
  contradicts `opt -run-twice`s own error message.

This patch fixes this as well.

Reviewed By: aprantl

Reviewers: loladiro, GorNishanov, espindola, echristo, dexonsmith

Subscribers: vsk, debug-info, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D45593

llvm-svn: 330069
2018-04-13 21:22:24 +00:00
Krzysztof Parzyszek
7c421b4ae9 [Hexagon] Initial instruction cost model for auto-vectorization
llvm-svn: 330065
2018-04-13 20:46:50 +00:00
Peter Collingbourne
82ccce4b49 Revert r329956, "AArch64: Introduce a DAG combine for folding offsets into addresses."
Caused a hang and eventually an assertion failure in LTO builds
of 7zip-benchmark on aarch64 iOS targets.
http://green.lab.llvm.org/green/job/lnt-ctmark-aarch64-O3-flto/2024/

llvm-svn: 330063
2018-04-13 20:21:00 +00:00
Krzysztof Parzyszek
ad72037b93 [LV] Introduce TTI::getMinimumVF
The function getMinimumVF(ElemWidth) will return the minimum VF for
a vector with elements of size ElemWidth bits. This value will only
apply to targets for which TTI::shouldMaximizeVectorBandwidth returns
true. The value of 0 indicates that there is no minimum VF.

Differential Revision: https://reviews.llvm.org/D45271

llvm-svn: 330062
2018-04-13 20:16:32 +00:00
Mandeep Singh Grang
f124c956c3 [DebugInfo] Change std::sort to llvm::sort in response to r327219
r327219 added wrappers to std::sort which randomly shuffle the container before
sorting.  This will help in uncovering non-determinism caused due to undefined
sorting order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of
std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to
llvm::sort.  Refer the comments section in D44363 for a list of all the
required patches.

llvm-svn: 330061
2018-04-13 19:50:51 +00:00
Stefan Pintilie
3404333aff [Power9] Add the TLS store instructions to the Power 9 model
The Power 9 scheduler model should now include the TLS instructions.
We can now, once again, mark the model as complete.
From now on, if instructions are added to Power 9 but are not
added to the model the build should produce an error. Hopefully
that will alert the developer who is adding new instructions
that they should also be added to the scheulder model.

llvm-svn: 330060
2018-04-13 19:49:58 +00:00
Mandeep Singh Grang
4e39759fa1 [Transforms] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.

Reviewers: kcc, pcc, danielcdh, jmolloy, sanjoy, dberlin, ruiu

Reviewed By: ruiu

Subscribers: ruiu, llvm-commits

Differential Revision: https://reviews.llvm.org/D45142

llvm-svn: 330059
2018-04-13 19:47:57 +00:00
Mandeep Singh Grang
2cdc47a3e2 [MC] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.

Reviewers: grosbach, void, ruiu

Reviewed By: ruiu

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45138

llvm-svn: 330058
2018-04-13 19:47:01 +00:00
Mandeep Singh Grang
28496b1621 [ProfileData] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.

Reviewers: bogner, vsk, eraman, ruiu

Reviewed By: ruiu

Subscribers: ruiu, llvm-commits

Differential Revision: https://reviews.llvm.org/D45139

llvm-svn: 330057
2018-04-13 19:46:36 +00:00
Simon Pilgrim
505b757968 [CostModel][X86] Add some specific cpu targets to the cost models
We're mostly testing with generic isa attributes, but PR36550 will require testing of specific target's scheduler models as well.

llvm-svn: 330056
2018-04-13 19:30:15 +00:00
Simon Pilgrim
54c1641ded [CostModel][X86] Split fma arith costs tests from other fp tests
Was proving cumbersome to test with/without fma

llvm-svn: 330054
2018-04-13 19:12:32 +00:00
Mandeep Singh Grang
bfeff10faa [LTO] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer D44363 for a list of all the required patches.

Reviewers: pcc, mehdi_amini, ruiu

Reviewed By: ruiu

Subscribers: ruiu, inglorion, eraman, llvm-commits

Differential Revision: https://reviews.llvm.org/D45137

llvm-svn: 330053
2018-04-13 19:12:20 +00:00
Simon Pilgrim
b69b89f739 [CostModel][X86] Regenerate latency/codesize cost tests
llvm-svn: 330052
2018-04-13 18:56:58 +00:00
Simon Pilgrim
5285365bcf [CostModel][X86] Regenerate cast conversion cost tests
llvm-svn: 330051
2018-04-13 18:56:05 +00:00
Simon Pilgrim
bde2cc84a7 [CostModel][X86] Regenerate masked intrinsic cost tests
llvm-svn: 330050
2018-04-13 18:54:16 +00:00
Rui Ueyama
04fb9911c5 Define InitLLVM to do common initialization all at once.
We have a few functions that virtually all command wants to run on
process startup/shutdown. This patch adds InitLLVM class to do that
all at once, so that we don't need to copy-n-paste boilerplate code
to each llvm command's main() function.

Differential Revision: https://reviews.llvm.org/D45602

llvm-svn: 330046
2018-04-13 18:26:06 +00:00
Andrey Konovalov
d4621776c9 hwasan: add -fsanitize=kernel-hwaddress flag
This patch adds -fsanitize=kernel-hwaddress flag, that essentially enables
-hwasan-kernel=1 -hwasan-recover=1 -hwasan-match-all-tag=0xff.

Differential Revision: https://reviews.llvm.org/D45046

llvm-svn: 330044
2018-04-13 18:05:21 +00:00
Roman Lebedev
6f45714809 [InstCombine][NFC] masked-merge: commutativity tests: ensure the ordering.
This was intended since initially, but i did not really think
about it, and did not know how to force that. Now that the
xor->or fold is working (patch upcoming), this came up
to improve the test coverage.

A followup for rL330003, rL330007
https://bugs.llvm.org/show_bug.cgi?id=6773

llvm-svn: 330039
2018-04-13 17:15:55 +00:00
Sean Fertile
b9556857d8 Add PPC64_GLINK dynamic tag.
Add support for the PPC64_GLINK dynamic tag which is used in the ElfV2 abi.

Differential Revision: https://reviews.llvm.org/D45574

llvm-svn: 330038
2018-04-13 16:42:48 +00:00
Simon Dardis
22bc24cee7 [mips] Materialize constants for multiplication
Previously, the MIPS backend would alwyas break down constant multiplications
into a series of shifts, adds, and subs. This patch changes that so the cost of
doing so is estimated.

The cost is estimated against worst case constant materialization and retrieving
the results from the HI/LO registers.

For cases where the value type of the multiplication is not legal, the cost of
legalization is estimated and is accounted for before performing the
optimization of breaking down the constant

This resolves PR36884.

Thanks to npl for reporting the issue!

Reviewers: abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D45316

llvm-svn: 330037
2018-04-13 16:09:07 +00:00
Simon Pilgrim
2b5704cadd [X86] Remove remaining itinerary support from instructions and target (PR37093)
llvm-svn: 330035
2018-04-13 15:37:56 +00:00
Sjoerd Meijer
b69b9d3362 [ARM] FP16 vmaxnm/vminnm scalar instructions
This adds code generation support for the FP16 vmaxnm/vminnm scalar
instructions.

Differential Revision: https://reviews.llvm.org/D44675

llvm-svn: 330034
2018-04-13 15:34:26 +00:00
Clement Courbet
f975577120 Revert r330027: "[llvm-exegesis] re-enable failing tests after r330026."
The tests are still failing on some bots.

llvm-svn: 330033
2018-04-13 15:19:16 +00:00
Andrea Di Biagio
8de05aaa85 [llvm-mca] Ensure that instructions with a schedule read-advance are always issued in the right order.
Normally, the Scheduler prioritizes older instructions over younger instructions
during the instruction issue stage. In one particular case where a dependent
instruction had a schedule read-advance associated to one of the input operands,
this rule was not correctly applied.

This patch fixes the issue and adds a test to verify that we don't regress that
particular case.

llvm-svn: 330032
2018-04-13 15:19:07 +00:00
Yan Luo
f63761c20a [ARC] Add LImm support for J/JL
llvm-svn: 330031
2018-04-13 15:10:34 +00:00
Simon Pilgrim
91deb0a497 [X86] Generalize X86FixupLEAs to work with TargetSchedModel
Similar to rL329834, don't rely on itinerary scheduler model to determine latencies for LEA thresholds, use the generic TargetSchedModel::computeInstrLatency call.

llvm-svn: 330030
2018-04-13 15:09:39 +00:00
Mircea Trofin
c08449efbb [profile] Fix binary format reader error propagation.
Summary:
This was originally part of rL328132, and led to the discovery
of the issues addressed in rL328987. Re-landing.

Reviewers: xur, davidxl, bkramer

Reviewed By: bkramer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45545

llvm-svn: 330029
2018-04-13 15:04:36 +00:00
Clement Courbet
c89aaddf9a [llvm-exegesis] re-enable failing tests after r330026.
llvm-svn: 330027
2018-04-13 14:50:10 +00:00
Clement Courbet
6c63e70e7b [llvm-exegesis] Fix use after free.
Reviewers: gchatelet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D45625

llvm-svn: 330026
2018-04-13 14:46:48 +00:00
Simon Pilgrim
de39a5c881 Remove comment reference to itineraries. NFCI.
llvm-svn: 330025
2018-04-13 14:42:48 +00:00
Sander de Smalen
4b82197a07 [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+imm) load instructions
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: rengolin

Subscribers: tschuett, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D45618

llvm-svn: 330024
2018-04-13 14:41:36 +00:00
Simon Pilgrim
2d3b6feea0 [X86][AVX512] UNPCKL/H PS and PD should be scheduled with WriteFShuffle not WriteFAdd
llvm-svn: 330023
2018-04-13 14:41:05 +00:00
Simon Pilgrim
2689540881 [X86] Remove remaining OpndItins/SizeItins from all instruction defs (PR37093)
llvm-svn: 330022
2018-04-13 14:36:59 +00:00
Simon Pilgrim
4d8c3742d4 Remove comment references to itineraries. NFCI.
llvm-svn: 330021
2018-04-13 14:31:57 +00:00
Clement Courbet
de862f240e [llvm-exegesis][NFC] Add more logging in case target creation fails.
llvm-svn: 330020
2018-04-13 14:29:52 +00:00
Simon Pilgrim
8dfff5935a Remove out of data comment. NFCI.
llvm-svn: 330019
2018-04-13 14:24:06 +00:00
Jun Bum Lim
8097873bb7 [PostRASink]Add register dependency check for implicit operands
Summary:
This change extend the register dependency check for implicit operands in Copy instructions.
Fixes PR36902.

Reviewers: thegameg, sebpop, uweigand, jnspaulsson, gberry, mcrosier, qcolombet, MatzeB

Reviewed By: thegameg

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D44958

llvm-svn: 330018
2018-04-13 14:23:09 +00:00
Roman Lebedev
1f5fecf693 [InstCombine][NFC] Regenerate logical-select.ll test
llvm-svn: 330017
2018-04-13 14:07:29 +00:00
Clement Courbet
1a9d61356a [llvm-exegesis] Create test files in temporary directory.
Currently the test fails in sandboxed environnements.

llvm-svn: 330015
2018-04-13 13:37:07 +00:00
Sander de Smalen
9f0017c23c [AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) store instructions.
Summary:
Added instructions for contiguous stores, ST1, with scalar+imm addressing
modes and corresponding tests. The patch also adds parsing of
'mul vl' as needed for the VL-scaled immediate.

This is patch [6/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: rengolin

Subscribers: tschuett, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D45432

llvm-svn: 330014
2018-04-13 12:56:14 +00:00
Simon Pilgrim
f11bee0ad9 [X86] Remove OpndItins/SizeItins from all sse instruction defs (PR37093)
llvm-svn: 330013
2018-04-13 12:50:31 +00:00
Ivan A. Kosarev
94f22e4959 [NEON] Support intrinsic for scalar and vector versions of the VRINTN instruction
Differential Revision: https://reviews.llvm.org/D45514

llvm-svn: 330011
2018-04-13 12:45:12 +00:00
Clement Courbet
7bc87a6a65 Partially revert r330008.
llvm-svn: 330010
2018-04-13 12:43:55 +00:00
Clement Courbet
e9da1f048c [llvm-exegesis] Run unit tests on more platforms.
Summary:
 - Target-independent tests are run all the time.
 - Tests that codegen X86 code are run when X86 is in build targets.
 - Tests that run X86 jitted code are run only on X86 hosts.

Reviewers: gchatelet

Subscribers: mgorny, llvm-commits, tschuett

Differential Revision: https://reviews.llvm.org/D45614

llvm-svn: 330008
2018-04-13 12:20:30 +00:00