Jim Grosbach
b09a003fa6
ARM NEON better assembly operand range checking for lane indices of VLD/VST.
...
llvm-svn: 146608
2011-12-14 23:35:06 +00:00
Jim Grosbach
75db252aee
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
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llvm-svn: 146605
2011-12-14 23:25:46 +00:00
Jim Grosbach
628ae663ef
ARM assembler support for the target-specific .req directive.
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rdar://10549683
llvm-svn: 146543
2011-12-14 02:16:11 +00:00
Jim Grosbach
089ad574d8
Thumb2 assembler aliases for "mov(shifted register)"
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rdar://10549767
llvm-svn: 146520
2011-12-13 22:45:11 +00:00
Jim Grosbach
bd33fc6efd
ARM LDM/STM system instruction variants.
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rdar://10550269
llvm-svn: 146519
2011-12-13 21:48:29 +00:00
Jim Grosbach
b2547b424c
Thumb2 tweak for ccout handling in RSB parsing.
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llvm-svn: 146516
2011-12-13 21:06:41 +00:00
Jim Grosbach
13d3509445
ARM thumb2 parsing of "rsb rd, rn, #0 ".
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rdar://10549741
llvm-svn: 146515
2011-12-13 20:50:38 +00:00
Jim Grosbach
1738a66371
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
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llvm-svn: 146508
2011-12-13 20:13:48 +00:00
Daniel Dunbar
30d6a45140
LLVMBuild: Remove trailing newline, which irked me.
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llvm-svn: 146409
2011-12-12 19:48:00 +00:00
Jim Grosbach
ece09e5e6b
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
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llvm-svn: 146300
2011-12-10 00:01:02 +00:00
Jim Grosbach
2356c1f141
ARM add some pre-UAL VFP mnemonics for convenience when porting old code.
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llvm-svn: 146296
2011-12-09 23:34:09 +00:00
Jim Grosbach
43cade9bb2
ARM allows '' syntax, not just '#imm' for assembly.
...
Backwards compatibility with 'gas'. #imm is the preferered and documented
syntax, but lots of existing code uses the '$' prefix, so we should
support it if we can.
llvm-svn: 146285
2011-12-09 22:25:03 +00:00
Jim Grosbach
5f3c519248
ARM convenience aliases for VSQRT.
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llvm-svn: 146201
2011-12-08 22:51:25 +00:00
Jim Grosbach
a33fa8aa88
ARM VSHR implied destination operand form aliases.
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llvm-svn: 146192
2011-12-08 22:06:06 +00:00
Jim Grosbach
01485b7e6e
ARM asm parser, just issue a warning for a duplicate reg in a list.
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For better 'gas' compatibility.
llvm-svn: 146185
2011-12-08 21:34:20 +00:00
Jim Grosbach
f79eacae90
ARM assembler support for register name aliases.
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rdar://10550084
llvm-svn: 146170
2011-12-08 19:27:38 +00:00
Jim Grosbach
e1fe053f6e
ARM NEON two-operand aliases for VSHL(immediate).
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llvm-svn: 146125
2011-12-08 01:30:04 +00:00
Jim Grosbach
597cb99d62
ARM VFP support 'fmrs/fmsr' aliases for 'vldr'
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llvm-svn: 146116
2011-12-08 00:52:55 +00:00
Jim Grosbach
fa73a483a9
ARM VFP support 'flds/fldd' aliases for 'vldr'
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llvm-svn: 146115
2011-12-08 00:49:29 +00:00
Jim Grosbach
c1cf417595
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
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llvm-svn: 146111
2011-12-08 00:31:07 +00:00
Jim Grosbach
6146f79b7d
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
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For 'gas' compatibility.
llvm-svn: 146106
2011-12-07 23:40:58 +00:00
Jim Grosbach
81cb9952c9
ARM support the .arm and .thumb directives for assembly mode switching.
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llvm-svn: 146042
2011-12-07 18:04:19 +00:00
Jim Grosbach
57478f4961
ARM: NEON SHLL instruction immediate operand range checking.
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llvm-svn: 146003
2011-12-07 01:07:24 +00:00
Jim Grosbach
8bdbe92631
Thumb2 encoding choice correction for PLD.
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Using encoding T1 for offset of #0 and encoding T2 for #-0.
rdar://10532413
llvm-svn: 145919
2011-12-06 04:49:29 +00:00
Jim Grosbach
74bbb6454e
Tweak ADDrr fix. Bad check for explicit .w
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llvm-svn: 145863
2011-12-05 22:27:04 +00:00
Jim Grosbach
898ab7e4ec
Thumb2 prefer ADD register encoding T2 to T3 when possible.
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rdar://10529664
llvm-svn: 145860
2011-12-05 22:16:39 +00:00
Jim Grosbach
655b017748
Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
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rdar://10529348
llvm-svn: 145851
2011-12-05 21:06:26 +00:00
Jim Grosbach
fb734dff3c
ARM NEON VEXT aliases for data type suffices.
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llvm-svn: 145726
2011-12-02 23:34:39 +00:00
Jim Grosbach
3b245f9c39
ARM VST1 single lane assembly parsing.
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llvm-svn: 145718
2011-12-02 22:34:51 +00:00
Jim Grosbach
82ae7f46ea
ARM VLD1 single lane assembly parsing.
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llvm-svn: 145712
2011-12-02 22:01:52 +00:00
Jim Grosbach
a568ef0db6
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
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Add the 16-bit lane variants while I'm at it.
llvm-svn: 145693
2011-12-02 18:52:30 +00:00
Jim Grosbach
d5c0c63223
ARM start parsing VLD1 single lane instructions.
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The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.
llvm-svn: 145655
2011-12-02 00:35:16 +00:00
Jim Grosbach
fa9f6ccd62
ARM parsing for VLD1 two register all lanes, no writeback.
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llvm-svn: 145504
2011-11-30 18:21:25 +00:00
Jim Grosbach
693ce8291c
ARM parsing aliases for VLD1 single register all lanes.
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llvm-svn: 145464
2011-11-30 01:09:44 +00:00
Jim Grosbach
9adabf4dde
Tidy up a bit.
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llvm-svn: 145458
2011-11-29 23:51:09 +00:00
Daniel Dunbar
4e00f5f8fd
build/CMake: Finish removal of add_llvm_library_dependencies.
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llvm-svn: 145420
2011-11-29 19:25:30 +00:00
Jim Grosbach
6007a95d57
Clean up debug printing of ARM shifted operands.
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llvm-svn: 144836
2011-11-16 21:46:50 +00:00
Jim Grosbach
18844fca8d
ARM assembly parsing for RRX mnemonic.
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rdar://9704684
llvm-svn: 144812
2011-11-16 19:05:59 +00:00
Jim Grosbach
acb7c2d555
ARM mode aliases for bitwise instructions w/ register operands.
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rdar://9704684
llvm-svn: 144803
2011-11-16 18:31:45 +00:00
Jim Grosbach
044acb8bee
ARM assembly parsing for register range syntax for VLD/VST register lists.
...
For example,
vld1.f64 {d2-d5}, [r2,:128]!
Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!
It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.
rdar://10451128
llvm-svn: 144727
2011-11-15 23:19:15 +00:00
Jim Grosbach
e991d79b50
ARM accept an immediate offset in memory operands w/o the '#'.
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llvm-svn: 144709
2011-11-15 22:14:41 +00:00
Jim Grosbach
8f360855cf
ARM enclosing curly braces optional on one-register VLD/VST instruction lists.
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'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]'
rdar://10450488.
llvm-svn: 144701
2011-11-15 21:45:55 +00:00
Jim Grosbach
f68b81adb7
Fix typo.
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llvm-svn: 144695
2011-11-15 21:01:30 +00:00
Jim Grosbach
6dbfffcbf7
Thumb2 two-operand 'mul' instruction wide encoding parsing.
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rdar://10449724
llvm-svn: 144684
2011-11-15 19:55:16 +00:00
Jim Grosbach
df951fa128
Thumb2 assembly parsing for mul.w in IT block fix.
...
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.
rdar://10449281
llvm-svn: 144679
2011-11-15 19:29:45 +00:00
Jim Grosbach
d791cf718c
Tidy up. 80 column.
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llvm-svn: 144538
2011-11-14 17:52:47 +00:00
Jim Grosbach
7e41554aa7
ARM refactor simple immediate asm operand render methods.
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These immediate operands all use the same simple logic for rendering to
MCInst, so have them share the method for doing so.
llvm-svn: 144439
2011-11-12 00:58:43 +00:00
Jim Grosbach
bc077320e1
ARM vldm and vstm VFP instructions can take a data type suffix.
...
It's ignored by the assembler when present, but is legal syntax. Other
instructions have something similar, but for some mnemonics it's
only sometimes not significant, so this quick check in the parser will
need refactored into something more robust soon-ish. This gets some
basics working in the meantime.
Partial for rdar://10435264
llvm-svn: 144422
2011-11-11 23:08:10 +00:00
Jim Grosbach
01a7117803
Nuke no longer accurate comment.
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llvm-svn: 144411
2011-11-11 22:30:06 +00:00
Jim Grosbach
1d581ecb00
ARM allow Q registers in vldm/vstm register lists.
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rdar://9672822
llvm-svn: 144407
2011-11-11 21:27:40 +00:00