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Commit Graph

42743 Commits

Author SHA1 Message Date
Chris Lattner
45c679522d stay out of the reserved namespace
llvm-svn: 117773
2010-10-30 04:57:14 +00:00
Chris Lattner
deabc3d7fa simplify this code.
llvm-svn: 117771
2010-10-30 04:35:59 +00:00
Chris Lattner
3a36dd4a0b split MaybeParseRegister into its two logical uses, eliminating malloc+free traffic.
llvm-svn: 117769
2010-10-30 04:09:10 +00:00
Jim Grosbach
298cac8db3 Avoid re-evaluating MI.getNumOperands() every iteration of the loop.
llvm-svn: 117766
2010-10-30 01:40:16 +00:00
Jakob Stoklund Olesen
b3b1db4e67 Include MachineBasicBlock numbers in viewCFG() output.
llvm-svn: 117765
2010-10-30 01:26:19 +00:00
Jakob Stoklund Olesen
035667c0d6 Make sure copies are inserted after any exception handling labels at the top of
a basic block.

llvm-svn: 117764
2010-10-30 01:26:16 +00:00
Jakob Stoklund Olesen
0ab92619d0 Add SkipPHIsAndLabels from PHIElimination to MachineBasicBlock. It is needed
elsewhere.

llvm-svn: 117763
2010-10-30 01:26:14 +00:00
Jakob Stoklund Olesen
b751dffc9f Disable more of physical register live intervals verification.
llvm-svn: 117762
2010-10-30 01:26:11 +00:00
Jakob Stoklund Olesen
4425035bfd Print out register class of spilled register.
llvm-svn: 117761
2010-10-30 01:26:09 +00:00
Bob Wilson
183c466006 Overhaul memory barriers in the ARM backend. Radar 8601999.
There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain.  It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions.  Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions.  Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.

llvm-svn: 117756
2010-10-30 00:54:37 +00:00
Jim Grosbach
996d1280bd Encode the register list operands for ARM mode LDM/STM instructions.
llvm-svn: 117753
2010-10-30 00:37:59 +00:00
Bill Wendling
b68e0d0ee3 Some instructions end with an "ls" prefix, but it doesn't indicate that they are
conditional. Check for those instructions explicitly.

llvm-svn: 117747
2010-10-29 23:50:21 +00:00
Evan Cheng
d81c33d91e Teach machine cse to eliminate instructions with multiple physreg uses and defs. rdar://8610857.
llvm-svn: 117745
2010-10-29 23:36:03 +00:00
Jim Grosbach
9a473e23b8 Remove hard tab characters.
llvm-svn: 117742
2010-10-29 23:23:15 +00:00
Jim Grosbach
7ca6ac347d 80 column fix.
llvm-svn: 117741
2010-10-29 23:21:57 +00:00
Jim Grosbach
038d376c59 trailing whitespace
llvm-svn: 117740
2010-10-29 23:21:03 +00:00
Jim Grosbach
7cf8dcc5bd s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operand
encoder functions.

llvm-svn: 117738
2010-10-29 23:19:55 +00:00
Evan Cheng
7695213793 Fix fpscr <-> GPR latency info.
llvm-svn: 117737
2010-10-29 23:16:55 +00:00
Rafael Espindola
0d9ac34ffa Be more strict on when we produce an undefined reference. In gas a file with
just

.type   foo,@object

will produce an undefined reference to foo. On the other hand, a file with
just

.weakref bar, foo

will not. It is somewhat hard to support both in MC since both statements
should create the symbols. It should be possible if we really need to by
adding to the flags, but hopefully that is not necessary.

With this patch we do not produce a undefined reference in any of those cases.
The assembly file needs an actual use for the undefined reference to be
present.

This is in preparation for a patch implementing .weakref.

llvm-svn: 117735
2010-10-29 23:09:31 +00:00
Bob Wilson
d84c4629c1 Clean up indentation and other whitespace.
llvm-svn: 117728
2010-10-29 22:20:45 +00:00
Bob Wilson
9297637759 Remove trailing whitespace.
llvm-svn: 117727
2010-10-29 22:20:43 +00:00
Bob Wilson
59dedc2629 Fix 80-column violation.
llvm-svn: 117722
2010-10-29 22:03:07 +00:00
Bob Wilson
d7f24e831f Change instcombine's getShuffleMask to represent undef with negative values.
This code had previously used 2*N, where N is the mask length, to represent
undef.  That is not safe because the shufflevector operands may have more
than N elements -- they don't have to match the result type.

llvm-svn: 117721
2010-10-29 22:03:05 +00:00
Bob Wilson
d67dddb134 Remove DAG combiner patch to fold vector splats. Instcombiner does it now.
llvm-svn: 117720
2010-10-29 22:03:02 +00:00
Bob Wilson
996353fb5d Make instcombine a little more aggressive in combining vector shuffles.
Allow splats even if they don't match either of the original shuffles,
possibly due to undef entries in the shuffles masks.  Radar 8597790.
Also fix some 80-column violations.

llvm-svn: 117719
2010-10-29 22:02:50 +00:00
Jim Grosbach
e811e91d02 add FIXME
llvm-svn: 117718
2010-10-29 21:56:51 +00:00
Jim Grosbach
fcfc42b7bb Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in
the ARMExpandPseudos pass rather than during the asm lowering.

llvm-svn: 117714
2010-10-29 21:35:25 +00:00
Eric Christopher
bf7cf2a203 Handle comparison values we already have - this fixes the consumer-typeset
failure for llvm-gcc on arm fast isel.

llvm-svn: 117710
2010-10-29 21:08:19 +00:00
Owen Anderson
b41f027059 Give up on doing in-line instruction simplification during correlated value propagation. Instruction simplification
needs to be guaranteed never to be run on an unreachable block.  However, earlier block simplifications may have
changed the CFG to make block that were reachable when we began our iteration unreachable by the time we try to
simplify them. (Note that this also means that our depth-first iterators were potentially being invalidated).

This should not have a large impact on code quality, since later runs of instcombine should pick up these simplifications.
Fixes PR8506.

llvm-svn: 117709
2010-10-29 21:05:17 +00:00
Jim Grosbach
93fbda05ee ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need to
handle it in the asm lowering.

llvm-svn: 117707
2010-10-29 20:37:06 +00:00
Jim Grosbach
52638aa1c8 Fix typo.
llvm-svn: 117703
2010-10-29 20:21:49 +00:00
Jim Grosbach
4ca61d9877 ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS.
llvm-svn: 117702
2010-10-29 20:21:36 +00:00
Dan Gohman
85557399a1 Make ScalarEvolution::forgetLoop forget all contained loops too, because
they may have ValuesAtScopes map entries referencing their outer loops.
This fixes a user-after-free reported in PR8471.

llvm-svn: 117698
2010-10-29 20:16:10 +00:00
Jim Grosbach
162e3345fb ARM mode LDREX*/STREX* binary encodings.
llvm-svn: 117695
2010-10-29 19:58:57 +00:00
Jim Grosbach
5bc94b46a9 Encoding information for ARM conditional move instructions.
llvm-svn: 117687
2010-10-29 19:28:17 +00:00
Jakob Stoklund Olesen
469a9ef414 Fix sign error.
llvm-svn: 117677
2010-10-29 18:21:18 +00:00
Evan Cheng
392d2cbdcc Avoiding overly aggressive latency scheduling. If the two nodes share an
operand and one of them has a single use that is a live out copy, favor the
one that is live out. Otherwise it will be difficult to eliminate the copy
if the instruction is a loop induction variable update. e.g.

BB:
sub r1, r3, #1
str r0, [r2, r3]
mov r3, r1
cmp
bne BB

=>

BB:
str r0, [r2, r3]
sub r3, r3, #1
cmp
bne BB

This fixed the recent 256.bzip2 regression.

llvm-svn: 117675
2010-10-29 18:09:28 +00:00
Evan Cheng
92293993bd - Don't schedule nodes with only MVT::Flag and MVT::Other values for latency.
- Compute CopyToReg use operand latency correctly.

llvm-svn: 117674
2010-10-29 18:07:31 +00:00
Jakob Stoklund Olesen
1f2fb9a020 Don't transfer unused values to the new intervals formed by splitting.
llvm-svn: 117673
2010-10-29 17:47:49 +00:00
Jim Grosbach
edec5cc6b8 Handle ARM addrmode5 instructions with an offset.
llvm-svn: 117672
2010-10-29 17:41:25 +00:00
Benjamin Kramer
d84e7a7b91 Silence Release build warnings.
llvm-svn: 117671
2010-10-29 17:40:05 +00:00
Jakob Stoklund Olesen
d56c4457a6 Teach ConnectedVNInfoEqClasses::Classify to deal with unused values.
We don't want unused values forming their own equivalence classes, so we lump
them all together in one class, and then merge them with the class of the last
used value.

llvm-svn: 117670
2010-10-29 17:37:29 +00:00
Jakob Stoklund Olesen
e577489ba5 Never propagate the idom value out of a block that defines its own value.
llvm-svn: 117669
2010-10-29 17:37:25 +00:00
John Thompson
6115a7f1d4 Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
llvm-svn: 117667
2010-10-29 17:29:13 +00:00
Dan Gohman
85403d8246 Check if ErrMsg is null. This fixes the "not" command.
llvm-svn: 117666
2010-10-29 17:20:42 +00:00
Dan Gohman
6a889e86df Fix these error messages to be less confusing. These error
messages primarily indicate errors running the viewer, not
errors with the graph file itself.

llvm-svn: 117665
2010-10-29 17:03:40 +00:00
Dan Gohman
b27988e5bd Make Program::Wait differentiate execution failure due to the file
being not found from the file being not executable. 

llvm-svn: 117664
2010-10-29 16:54:25 +00:00
Jim Grosbach
6f257bd31b Revert 117660. Apparently it's not as trivial as that...
llvm-svn: 117663
2010-10-29 16:50:53 +00:00
Dan Gohman
a80b1afde3 Make Program::Wait provide an error message string for errors
executing the child process and abnormal child process termination.

llvm-svn: 117661
2010-10-29 16:39:01 +00:00
Jim Grosbach
8c9a2ee86e ARM addrmode5 instructions have neither writeback nor post-indexed modes.
llvm-svn: 117660
2010-10-29 16:38:59 +00:00
Jim Grosbach
29961ebfc5 Trailing whitespace.
llvm-svn: 117651
2010-10-29 14:46:02 +00:00
Benjamin Kramer
f2442da5f6 ARMAsmParser: Plug a memory leak.
llvm-svn: 117648
2010-10-29 09:43:39 +00:00
Eric Christopher
930a767468 Add an unreachable to silence warning - the switch is actually
fully enumerated.

llvm-svn: 117647
2010-10-29 09:26:59 +00:00
Bill Wendling
d9412db2c8 This may be an ARM target, so check for _Unwind_SjLj_Resume.
llvm-svn: 117643
2010-10-29 07:46:01 +00:00
Dan Gohman
753c9ce807 Teach memdep to use pointsToConstantMemory to determine that loads
from constant memory don't alias any stores.

llvm-svn: 117636
2010-10-29 01:14:04 +00:00
Jakob Stoklund Olesen
b7a4b7a7b0 Fix broken equivalence class calculation. We could probably also use
EquvivalenceClasses.h except it looks like overkill when elements are continuous
integers.

llvm-svn: 117631
2010-10-29 00:40:59 +00:00
Jakob Stoklund Olesen
1210a5145a Print out the connected components in the verifier after complaining about their
multiplicity.

llvm-svn: 117630
2010-10-29 00:40:57 +00:00
Jakob Stoklund Olesen
e446520687 Run a verification pass before any splitting to better distribute blame.
llvm-svn: 117629
2010-10-29 00:40:55 +00:00
Chris Lattner
115cd02d22 add simple support for addrmode5 operands, allowing
vldr.64 to work.  I have no idea if this is fully right, but 
it is in the right direction.

llvm-svn: 117626
2010-10-29 00:27:31 +00:00
Devang Patel
bf9c3c8947 Ignore empty blocks.
llvm-svn: 117615
2010-10-28 22:11:59 +00:00
Chris Lattner
ef237e6013 give better error diagnostics, for example:
t.s:1:14: error: invalid operand for instruction
vldr.64	d17, [r0]   
       	     ^

instead of:

t.s:1:1: error: unrecognized instruction
vldr.64	d17, [r0]   
^

llvm-svn: 117611
2010-10-28 21:41:58 +00:00
Chris Lattner
ba1e908431 hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes
the opcode string in the inst dump, e.g.:
	vmov	r2, r3, d17             @ encoding: [0x31,0x2b,0x53,0xec]
                                        @ <MCInst #989 VMOVRRD
                                        @  <MCOperand Reg:68>
                                        @  <MCOperand Reg:69>
                                        @  <MCOperand Reg:19>
                                        @  <MCOperand Imm:14>
                                        @  <MCOperand Reg:0>>

The "VMOVRRD" is new.

llvm-svn: 117609
2010-10-28 21:37:33 +00:00
Rafael Espindola
913ce7ebc8 Improvements to .section parsing:
* If we have a M or a G, reject sections without the type
* Only parse the flag specific arguments if we have M or G
* Parse the corresponding arguments for M and G

We ignore the G arguments and flag for now.

llvm-svn: 117608
2010-10-28 21:33:33 +00:00
Chris Lattner
4210ffb9c5 move a method out of line.
llvm-svn: 117605
2010-10-28 21:28:01 +00:00
Chris Lattner
b6c7a9e204 remove the rest of hte owningptr's, no functionality change.
llvm-svn: 117603
2010-10-28 20:52:15 +00:00
Jakob Stoklund Olesen
c570151dc2 One day, physical register live ranges will be sensible.
llvm-svn: 117602
2010-10-28 20:44:22 +00:00
Jakob Stoklund Olesen
ccbfbefd93 Replace SplitKit SSA update with an iterative algorithm very similar to the one
in SSAUpdaterImpl.h

Verifying live intervals revealed that the old method was completely wrong, and
we need an iterative approach to calculating PHI placemant. Fortunately, we have
MachineDominators available, so we don't have to compute that over and over
like SSAUpdaterImpl.h must.

Live-out values are cached between calls to mapValue() and computed in a greedy
way, so most calls will be working with very small block sets.

Thanks to Bob for explaining how this should work.

llvm-svn: 117599
2010-10-28 20:34:52 +00:00
Jakob Stoklund Olesen
6f4262448e Make MachineDominators available for SplitEditor. We are going to need it for
proper SSA updating.

This doesn't cause MachineDominators to be recomputed since we are already
requiring MachineLoopInfo which uses dominators as well.

llvm-svn: 117598
2010-10-28 20:34:50 +00:00
Jakob Stoklund Olesen
35f9c58245 Add a temporary command line option to verify machine code after each spill or
split.

llvm-svn: 117597
2010-10-28 20:34:47 +00:00
Dan Gohman
d512ed689c Revert r117582, which reverted r77396. Searching PATH for a string
which contains slashes is inconsistent with the meaning of PATH on
Unix-type platforms, and pretty surprising.

If the user has given a specific path to execute and we can't
execute it, we should fail and say why.  (Apparently the new
posix_spawn code doesn't always say why, but that's a separate
issue.)

llvm-svn: 117596
2010-10-28 20:34:33 +00:00
Rafael Espindola
b562975139 Add support for the .string directive.
llvm-svn: 117592
2010-10-28 20:02:27 +00:00
Devang Patel
a496603faf Do not work too hard to find type's file info. There is a special field to record file info.
llvm-svn: 117588
2010-10-28 19:50:08 +00:00
Rafael Espindola
f230319275 Defined weak symbols should have non-zero value.
llvm-svn: 117585
2010-10-28 19:39:57 +00:00
Mikhail Glushenkov
8988adb7db llvmc: Make ExecuteProgram() look in the driver directory first.
llvm-svn: 117584
2010-10-28 19:33:08 +00:00
Mikhail Glushenkov
7ee0f678cb Remove an unnecessary check and an unnecessary temporary.
llvm-svn: 117583
2010-10-28 19:33:04 +00:00
Mikhail Glushenkov
b727c53cff Revert r77396.
Original commit message:

    On "Unix", if Program::FindProgramByName is given a name containing
    slashes, just go with it, regardless of whether it looks like it will
    be executable. This follows the behavior of sh(1) more closely.

It's better when behaviour is consistent between platforms. This change also
makes FindExecutable() behave as expected on unix-likes (before this commit, it
used to always succeed).

llvm-svn: 117582
2010-10-28 19:32:58 +00:00
Mikhail Glushenkov
e2c628c84f Trailing whitespace.
llvm-svn: 117581
2010-10-28 19:32:53 +00:00
Rafael Espindola
862d688cbd Fix relocations with renamed symbols.
llvm-svn: 117575
2010-10-28 19:08:03 +00:00
Benjamin Kramer
fbfb8cf5f8 Reduce malloc thrashing.
llvm-svn: 117572
2010-10-28 18:41:23 +00:00
Jim Grosbach
d02c1c7d77 PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.
llvm-svn: 117571
2010-10-28 18:34:10 +00:00
Rafael Espindola
e62cf892ae Aliases defined with .symver should copy the binding of the symbols they alias.
Move the existing patching for undefined symbols so that all the patching
is done in the same function.

llvm-svn: 117570
2010-10-28 18:33:03 +00:00
Devang Patel
0e43a2d84f Technically DIFile scope should also be handled here.
llvm-svn: 117563
2010-10-28 17:30:52 +00:00
Chris Lattner
0a21ad2553 rearrange ParseRegisterList.
llvm-svn: 117560
2010-10-28 17:23:41 +00:00
Chris Lattner
a9c0f00f10 refactor some code to simplify it, eliminating some owningptr's.
llvm-svn: 117559
2010-10-28 17:20:03 +00:00
Bob Wilson
65124cd7c7 Teach the DAG combiner to fold a splat of a splat. Radar 8597790.
Also do some minor refactoring to reduce indentation.

llvm-svn: 117558
2010-10-28 17:06:14 +00:00
Roman Divacky
2aedee6ff2 Use the IDVal directly as there's no need to convert to std::string.
Pointed out by Chris!

llvm-svn: 117557
2010-10-28 16:57:58 +00:00
Roman Divacky
8555f153e9 Implement .equ directive as a synonym to .set.
llvm-svn: 117553
2010-10-28 16:22:58 +00:00
Duncan Sands
eccf0b18a5 Fix PR8494: when reading invalid bitcode, getTypeByID may return
a null pointer.

llvm-svn: 117551
2010-10-28 15:47:26 +00:00
Rafael Espindola
ff7e4e4e43 Implement R_X86_64_DTPOFF32.
llvm-svn: 117548
2010-10-28 15:11:03 +00:00
Rafael Espindola
1d1ff5485c Implement TLSLD.
llvm-svn: 117547
2010-10-28 15:02:40 +00:00
Rafael Espindola
8372247e83 Implement DTPOFF.
llvm-svn: 117546
2010-10-28 14:48:59 +00:00
Rafael Espindola
c44c5b374a Implement TLSLDM.
llvm-svn: 117544
2010-10-28 14:37:09 +00:00
Rafael Espindola
d8ef67f8b9 Implement VK_GOTNTPOFF and switch RelocNeedsGOT to use VariantKind.
llvm-svn: 117543
2010-10-28 14:22:44 +00:00
Mikhail Glushenkov
4bf08b3a06 Reindent.
llvm-svn: 117538
2010-10-28 08:25:44 +00:00
Evan Cheng
bc4588c439 Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.
llvm-svn: 117531
2010-10-28 06:47:08 +00:00
Evan Cheng
fdc80a0316 Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh.
llvm-svn: 117520
2010-10-28 02:00:25 +00:00
Evan Cheng
5c358e02ea - Assign load / store with shifter op address modes the right itinerary classes.
- For now, loads of [r, r] addressing mode is the same as the
  [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
  identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
  is "free".

llvm-svn: 117519
2010-10-28 01:49:06 +00:00
Evan Cheng
a07cd58978 Fix a major bug in operand latency computation. The use index must be adjusted
by the number of defs first for it to match the instruction itinerary.

llvm-svn: 117518
2010-10-28 01:46:29 +00:00
Dale Johannesen
b78530f9b0 Fix pastos in handling of AVX cvttsd2si, PR8491.
Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!

llvm-svn: 117514
2010-10-28 00:35:54 +00:00
Owen Anderson
e75f7c5419 Add correct NEON encodings for vtbl and vtbx.
llvm-svn: 117513
2010-10-28 00:18:46 +00:00