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b15f862d86
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19949 Commits

Author SHA1 Message Date
Jim Grosbach
b15f862d86 ARM VEXT tighten up operand classes a bit. 
llvm-svn: 145722
 2011-12-02 22:57:57 +00:00
Jim Grosbach
3b245f9c39 ARM VST1 single lane assembly parsing. 
llvm-svn: 145718
 2011-12-02 22:34:51 +00:00
Nick Lewycky
7d0d3c2d58 Move global variables in TargetMachine into new TargetOptions class. As an API 
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.

One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.

llvm-svn: 145714
 2011-12-02 22:16:29 +00:00
Jim Grosbach
82ae7f46ea ARM VLD1 single lane assembly parsing. 
llvm-svn: 145712
 2011-12-02 22:01:52 +00:00
Jim Grosbach
cbde5d4877 ARM encoder method needs the physical register number, not the enum. 
llvm-svn: 145711
 2011-12-02 22:01:25 +00:00
Chad Rosier
b3b2871bbf [arm-fast-isel] After promoting a function parameter be sure to update the 
argument value type.  Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467

llvm-svn: 145701
 2011-12-02 20:25:18 +00:00
Jim Grosbach
a568ef0db6 Clean up aliases for ARM VLD1 single-lane assembly parsing a bit. 
Add the 16-bit lane variants while I'm at it.

llvm-svn: 145693
 2011-12-02 18:52:30 +00:00
Jan Sjödin
81ee97461c Add XOP feature flag. 
llvm-svn: 145682
 2011-12-02 15:14:37 +00:00
Craig Topper
c67b7d7e2c Reduce duplicate code in isHorizontalBinOp and add some asserts to protect assumptions 
llvm-svn: 145681
 2011-12-02 08:18:41 +00:00
Craig Topper
d381116357 Add instruction selection support for horizontal add/sub of 256-bit floating point vectors. Also add the test case for 256-bit integer vectors. 
llvm-svn: 145680
 2011-12-02 07:16:01 +00:00
Hal Finkel
c90c9f608e remove unneeded FIXME comment 
llvm-svn: 145679
 2011-12-02 04:58:17 +00:00
Hal Finkel
e0f1d3fc22 update PPC 940 hazard rec. to function in postRA mode 
llvm-svn: 145676
 2011-12-02 04:58:02 +00:00
Jim Grosbach
d5c0c63223 ARM start parsing VLD1 single lane instructions. 
The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.

llvm-svn: 145655
 2011-12-02 00:35:16 +00:00
Sanjoy Das
5cc5730434 Dummy commit to check commit access. 
llvm-svn: 145619
 2011-12-01 19:15:08 +00:00
Chad Rosier
aafbda2d54 Add missing functions. 
llvm-svn: 145608
 2011-12-01 18:26:19 +00:00
Chad Rosier
7610c57a02 Add a few more functions to TargetLibraryInfo. More of rdar://10500969. 
llvm-svn: 145596
 2011-12-01 17:54:37 +00:00
Eric Christopher
4aa8024569 For 64-bit the rest of the general regs are ok for the q constraint. Make 
sure we can emit both the high and low versions of those registers.

Fixes rdar://10392864

llvm-svn: 145579
 2011-12-01 08:12:41 +00:00
Eli Friedman
ad916965a6 Pass AVX vectors which are arguments to varargs functions on the stack. <rdar://problem/10463281>. 
llvm-svn: 145573
 2011-12-01 04:49:21 +00:00
Eli Friedman
85c0054183 Small fix for assembler generation on Darwin PPC64. Patch by Michael Kostylev. PR11437. 
llvm-svn: 145553
 2011-12-01 01:43:47 +00:00
Jan Sjödin
2dfb343ffa Support for encoding all FMA4 instructions and tablegen patterns for all 
remaining FMA4 instructions and intrinsics with tests.

llvm-svn: 145525
 2011-11-30 22:09:42 +00:00
Matt Beaumont-Gay
07afe588d4 Remove unused variable 
llvm-svn: 145517
 2011-11-30 19:53:11 +00:00
Jim Grosbach
6b2f6389cc ARM parsing for VLD1 all lanes, with writeback. 
llvm-svn: 145510
 2011-11-30 19:35:44 +00:00
Chad Rosier
8c6d695c1e Add a few functions to TargetLibraryInfo. 
llvm-svn: 145508
 2011-11-30 19:19:00 +00:00
Jim Grosbach
fa9f6ccd62 ARM parsing for VLD1 two register all lanes, no writeback. 
llvm-svn: 145504
 2011-11-30 18:21:25 +00:00
Benjamin Kramer
fbdf17c667 X86: Turns out bulldozer also supports sse42 and lzcnt. 
While at it remove the barcelona/instanbul/shanghai subtargets, they're
unsupported by GCC and look pretty broken.

llvm-svn: 145494
 2011-11-30 15:48:16 +00:00
Benjamin Kramer
359fde3539 X86: Add subtargets for AMD's bulldozer. 
llvm-svn: 145493
 2011-11-30 15:27:46 +00:00
Nadav Rotem
f8e096f4ee X86: PerformOrCombine introduced a vselect node with a wrong order of operands. This bug was introduced when a dedicated blend sdnode was replaced with the vselect node (in 139479). 
llvm-svn: 145488
 2011-11-30 10:13:37 +00:00
Craig Topper
2a0fc05456 Add instruction selection support for AVX2 horizontal add/sub instructions. 
llvm-svn: 145487
 2011-11-30 09:10:50 +00:00
Craig Topper
0ac9bb8aa1 Merge VPERM2F128/VPERM2I128 ISD node types. 
llvm-svn: 145485
 2011-11-30 07:47:51 +00:00
Craig Topper
43b885cff4 Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node type for VPERMILPD/PS. Add instruction selection support for VINSERTI128/VEXTRACTI128. 
llvm-svn: 145483
 2011-11-30 06:25:25 +00:00
Chad Rosier
8b15aca551 Alphabetize TargetLibraryInfo enum and fix doxygen comments. No functional 
change intended.

llvm-svn: 145468
 2011-11-30 01:51:49 +00:00
Jim Grosbach
693ce8291c ARM parsing aliases for VLD1 single register all lanes. 
llvm-svn: 145464
 2011-11-30 01:09:44 +00:00
Chad Rosier
c5fa9f413a Add support for sqrt, sqrtl, and sqrtf in TargetLibraryInfo. Disable 
(fptrunc (sqrt (fpext x))) -> (sqrtf x) transformation if -fno-builtin is 
specified.
rdar://10466410

llvm-svn: 145460
 2011-11-29 23:57:10 +00:00
Jim Grosbach
9adabf4dde Tidy up a bit. 
llvm-svn: 145458
 2011-11-29 23:51:09 +00:00
Jim Grosbach
ccc984051d Add comment. 
llvm-svn: 145456
 2011-11-29 23:33:40 +00:00
Jim Grosbach
29147b45a5 ARM parsing aliases for data-size suffices on VST1. 
llvm-svn: 145454
 2011-11-29 23:21:31 +00:00
Akira Hatanaka
fd548b69f5 Change names for MIPS "generic" processors defined in Mips.td to match what GNU 
tools use. Patch by Simon Atanasyan.

"mips32r1" => "mips32"
"4ke" => mips32r2"
"mips64r1" => "mips64"

llvm-svn: 145451
 2011-11-29 23:08:41 +00:00
Jim Grosbach
538759efa7 ARM assembly parsing and encoding for four-register VST1. 
llvm-svn: 145450
 2011-11-29 22:58:48 +00:00
Evan Cheng
5c1efd630b Add another missing pattern. llvm-gcc likes f64 but clang likes i64 so it was generating poor code for some SSE builtins. 
llvm-svn: 145448
 2011-11-29 22:48:34 +00:00
Jim Grosbach
5418e87582 ARM assembly parsing and encoding for three-register VST1. 
llvm-svn: 145442
 2011-11-29 22:38:04 +00:00
Jakob Stoklund Olesen
5d6a4584d9 Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions. 
Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.

This also makes the AVX variants redundant.

llvm-svn: 145440
 2011-11-29 22:27:25 +00:00
Andrew Trick
a6c63bda2e comment. 
llvm-svn: 145422
 2011-11-29 19:33:49 +00:00
Daniel Dunbar
4e00f5f8fd build/CMake: Finish removal of add_llvm_library_dependencies. 
llvm-svn: 145420
 2011-11-29 19:25:30 +00:00
Michael J. Spencer
5fade79478 MC/X86/COFF: Allow quotes in names when targeting MS/Windows, 
as MC is the only assembler we support.

This splits MS/Windows and GNU/Windows ASM infos into two seperate classes.
While there is currently only one difference, full MS C++ ABI support will
require many more.

llvm-svn: 145409
 2011-11-29 18:00:06 +00:00
Elena Demikhovsky
735cff1fa8 Fixed vsqrt.ss intrinsic usage - order of input operands was wrong. 
Added a test.
Thanks Bruno for reviewing the patch.

llvm-svn: 145403
 2011-11-29 15:00:45 +00:00
Craig Topper
637e60afdd Fix shuffle decoding for memory forms for (V)SHUFPS/D. 
llvm-svn: 145392
 2011-11-29 07:58:09 +00:00
Craig Topper
4550fc2649 Fix issues in shuffle decoding around VPERM* instructions. Fix shuffle decoding for VSHUFPS/D for 256-bit types. Add pattern matching for memory forms of VPERMILPS/VPERMILPD. 
llvm-svn: 145390
 2011-11-29 07:49:05 +00:00
Craig Topper
aca91b9f14 Fix VINSERTF128/VEXTRACTF128 to be marked as FP instructions. Allow execution dependency fix pass to convert them to their integer equivalents when AVX2 is enabled. 
llvm-svn: 145376
 2011-11-29 05:37:58 +00:00
Craig Topper
a6c1d25798 Correctly mark VPERM2F128 as being an FP instruction and add execution domain fixing support to convert it to VPERM2I128 for AVX2. 
llvm-svn: 145370
 2011-11-29 03:57:34 +00:00
Jim Grosbach
168778090c Better fix for ARM MOVT relocation encoding of thumb bit. 
Replaces r145318 with a more targetted fix for the relocation handling.

llvm-svn: 145346
 2011-11-29 01:15:25 +00:00