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Author SHA1 Message Date
David Blaikie
b1e1db3db6 DebugInfo: Don't lose unreferenced non-trivial by-value parameters 
A FastISel optimization was causing us to emit no information for such
parameters & when they go missing we end up emitting a different
function type. By avoiding that shortcut we not only get types correct
(very important) but also location information (handy) - even if it's
only live at the start of a function & may be clobbered later.

Reviewed/discussion by Evan Cheng & Dan Gohman.

llvm-svn: 184604
 2013-06-21 22:56:30 +00:00
Justin Holewinski
26b66eafe7 [NVPTX] Add support for selecting CUDA vs OCL mode based on triple 
IR for CUDA should use "nvptx[64]-nvidia-cuda", and IR for NV OpenCL should use "nvptx[64]-nvidia-nvcl"

llvm-svn: 184579
 2013-06-21 18:51:49 +00:00
Andrew Trick
3586872214 Fix IMULX machine model. Multiple def operands require multiple SchedWrites. 
llvm-svn: 184566
 2013-06-21 18:33:04 +00:00
Ulrich Weigand
3720d45002 [PowerPC] Support R_PPC_REL16 family of relocations 
The GNU assembler supports (as extension to the ABI) use of PC-relative
relocations in half16 fields, which allows writing code like:

  li 1, base-.

This patch adds support for those relocation types in the assembler.

llvm-svn: 184552
 2013-06-21 14:44:37 +00:00
Ulrich Weigand
d5bb2945ff [PowerPC] Support various tls-related modifiers 
The current code base only supports the minimum set of tls-related
relocations and @modifiers that are necessary to support compiler-
generated code.  This patch extends this to the full set defined
in the ABI (and supported by the GNU assembler) for the benefit
of the assembler parser.

llvm-svn: 184551
 2013-06-21 14:44:15 +00:00
Ulrich Weigand
325653d5a4 [PowerPC] Support @higher et.al. modifiers 
This adds support for the @higher, @highera, @highest, and @highesta
modifers, including some missing relocation types.

llvm-svn: 184550
 2013-06-21 14:43:42 +00:00
Ulrich Weigand
283132010a [PowerPC] Support @toc@h modifier 
This adds the relocation type and other necessary infrastructure
to use the @toc@h modifier in the assembler.

llvm-svn: 184549
 2013-06-21 14:43:10 +00:00
Ulrich Weigand
02d460319a [PowerPC] Support @h modifier 
This adds necessary infrastructure to support the @h modifier.
Note that all required relocation types were already present
(and unused).

This patch provides support for using @h in the assembler;
it would also be possible to now use this feature in code
generated by the compiler, but this is not done yet.

llvm-svn: 184548
 2013-06-21 14:42:49 +00:00
Ulrich Weigand
1b20b9f662 [PowerPC] Rename some more VK_PPC_ enums 
This renames more VK_PPC_ enums, to make them more closely reflect
the @modifier string they represent.  This also prepares for adding
a bunch of new VK_PPC_ enums in upcoming patches.

For consistency, some MO_ flags related to VK_PPC_ enums are
likewise renamed.

No change in behaviour.

llvm-svn: 184547
 2013-06-21 14:42:20 +00:00
Quentin Colombet
bdb6bfd975 ARM: Remove a (false) dependency on the memoryoperand's value as we do not use 
it at the moment.
This allows to form more paired loads even when stack coloring pass destroys the
memoryoperand's value.

<rdar://problem/13978317>

llvm-svn: 184492
 2013-06-20 22:51:44 +00:00
Ulrich Weigand
cd7cbdb152 [PowerPC] Clean up VK_PPC_TOC... names 
This is another minor cleanup; to bring enum names in line
with the corresponding @modifier names, this renames:

  VK_PPC_TOC -> VK_PPC_TOCBASE
  VK_PPC_TOC_ENTRY -> VK_PPC_TOC16

No code change intended.

llvm-svn: 184491
 2013-06-20 22:39:42 +00:00
Kevin Enderby
b71a2e2f2e Update the X86 disassembler to use xacquire and xrelease when appropriate. 
This is a bit tricky as the xacquire and xrelease hints use the same bytes,
0xf2 and 0xf3, as the repne and rep prefixes.

Fortunately llvm has different llvm MCInst Opcode enums for rep/xrelease
and repne/xacquire. So to make this work a boolean was added the
InternalInstruction struct as part of the Prefix state which is set with the
added logic in readPrefixes() when decoding an instruction to determine
if these prefix bytes are to be disassembled as xacquire or xrelease.  Then
we let the matcher pick the normal prefix instructionID and we change the
Opcode after that when it is set into the MCInst being created.

rdar://11019859

llvm-svn: 184490
 2013-06-20 22:32:18 +00:00
Ulrich Weigand
4de6b60db1 [PowerPC] Minor cleanup in PPCELFObjectWriter::getRelocTypeInner 
This just re-sorts the big switch statement in
PPCELFObjectWriter::getRelocTypeInner to follow
the (numerical) order of the reloc types, and
fixes a couple of whitespace issues.

llvm-svn: 184485
 2013-06-20 22:04:40 +00:00
Tom Stellard
a1d0e771db R600/SI: Expand sub for v2i32 and v4i32 for SI 
Also add a v2i32 test to the existing v4i32 test.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry<awatry@gmail.com>
llvm-svn: 184482
 2013-06-20 21:55:37 +00:00
Tom Stellard
c419716668 R600/SI: Expand add for v2i32 and v4i32 
Also add SI tests to existing file and a v2i32 test for both
R600 and SI.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 184481
 2013-06-20 21:55:30 +00:00
Tom Stellard
a6ec00250a R600: Expand v2i32 load/store instead of custom lowering 
The custom lowering causes llc to crash with a segfault.

Ideally, the custom lowering can be fixed, but this allows
programs which load/store v2i32 to work without crashing.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry<awatry@gmail.com>
llvm-svn: 184480
 2013-06-20 21:55:23 +00:00
Joey Gouly
a600985f50 This reverts r155000. 
The cdp2 instruction should have the same restrictions as cdp on the
co-processor registers.

VFP instructions on v8/AArch32 share the same encoding space as cdp2.

llvm-svn: 184445
 2013-06-20 17:42:36 +00:00
Ulrich Weigand
502b057268 [PowerPC] Remove unused parameter 
The isDarwin parameter to the llvm::LowerPPCMachineInstrToMCInst
routine is now no longer needed; remove it.

llvm-svn: 184441
 2013-06-20 16:58:14 +00:00
Ulrich Weigand
4cd8a01569 [PowerPC] Add missing build dependency 
This (hopefully) fixes build failures resulting from r184436;
the PowerPC asm parser now depends on PowerPC target expresssions.

llvm-svn: 184439
 2013-06-20 16:38:00 +00:00
Ulrich Weigand
99f0423d50 [PowerPC] Optimize @ha/@l constructs 
This patch adds support for having the assembler optimize fixups
to constructs like "symbol@ha" or "symbol@l" if "symbol" can be
resolved at assembler time.

This optimization is already present in the PPCMCExpr.cpp code
for handling PPC_HA16/PPC_LO16 target expressions.  However,
those target expression were used only on Darwin targets.

This patch changes target expression code so that they are
usable also with the GNU assembler (using the @ha / @l syntax
instead of the ha16() / lo16() syntax), and changes the
MCInst lowering code to generate those target expressions
where appropriate.

It also changes the asm parser to generate HA16/LO16 target
expressions when parsing assembler source that uses the
@ha / @l modifiers.  The effect is that now the above-
mentioned optimization automatically becomes available
for those situations too.
 

llvm-svn: 184436
 2013-06-20 16:23:52 +00:00
Ulrich Weigand
e143b13aca [PowerPC] Support compare mnemonics with implied CR0 
Just like for branch mnemonics (where support was recently added), the
assembler is supposed to support extended mnemonics for the compare
instructions where no condition register is specified explicitly
(and CR0 is assumed implicitly).

This patch adds support for those extended compare mnemonics.


Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
===================================================================
--- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s
+++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -449,21 +449,37 @@
 
 # CHECK: cmpdi 2, 3, 128                 # encoding: [0x2d,0x23,0x00,0x80]
          cmpdi 2, 3, 128
+# CHECK: cmpdi 0, 3, 128                 # encoding: [0x2c,0x23,0x00,0x80]
+         cmpdi 3, 128
 # CHECK: cmpd 2, 3, 4                    # encoding: [0x7d,0x23,0x20,0x00]
          cmpd 2, 3, 4
+# CHECK: cmpd 0, 3, 4                    # encoding: [0x7c,0x23,0x20,0x00]
+         cmpd 3, 4
 # CHECK: cmpldi 2, 3, 128                # encoding: [0x29,0x23,0x00,0x80]
          cmpldi 2, 3, 128
+# CHECK: cmpldi 0, 3, 128                # encoding: [0x28,0x23,0x00,0x80]
+         cmpldi 3, 128
 # CHECK: cmpld 2, 3, 4                   # encoding: [0x7d,0x23,0x20,0x40]
          cmpld 2, 3, 4
+# CHECK: cmpld 0, 3, 4                   # encoding: [0x7c,0x23,0x20,0x40]
+         cmpld 3, 4
 
 # CHECK: cmpwi 2, 3, 128                 # encoding: [0x2d,0x03,0x00,0x80]
          cmpwi 2, 3, 128
+# CHECK: cmpwi 0, 3, 128                 # encoding: [0x2c,0x03,0x00,0x80]
+         cmpwi 3, 128
 # CHECK: cmpw 2, 3, 4                    # encoding: [0x7d,0x03,0x20,0x00]
          cmpw 2, 3, 4
+# CHECK: cmpw 0, 3, 4                    # encoding: [0x7c,0x03,0x20,0x00]
+         cmpw 3, 4
 # CHECK: cmplwi 2, 3, 128                # encoding: [0x29,0x03,0x00,0x80]
          cmplwi 2, 3, 128
+# CHECK: cmplwi 0, 3, 128                # encoding: [0x28,0x03,0x00,0x80]
+         cmplwi 3, 128
 # CHECK: cmplw 2, 3, 4                   # encoding: [0x7d,0x03,0x20,0x40]
          cmplw 2, 3, 4
+# CHECK: cmplw 0, 3, 4                   # encoding: [0x7c,0x03,0x20,0x40]
+         cmplw 3, 4
 
 # FIXME: Trap mnemonics
 
Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>;
 defm : BranchExtendedMnemonic<"nu", 100>;
 defm : BranchExtendedMnemonic<"ns", 100>;
 
+def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
+

llvm-svn: 184435
 2013-06-20 16:15:12 +00:00
Vladimir Medic
af5979fc83 Optimize register parsing for MipsAsmParser. Allow symbolic aliases for FPU registers. 
llvm-svn: 184411
 2013-06-20 11:21:49 +00:00
Bill Wendling
49f45f9861 Don't pass in the TargetInstrInfo into the register info object. It doesn't use it. 
llvm-svn: 184369
 2013-06-19 21:59:00 +00:00
David Blaikie
c3cec14be6 DebugInfo: PR14763/r183329 correct the location of indirect parameters 
We had been papering over a problem with location info for non-trivial
types passed by value by emitting their type as references (this caused
the debugger to interpret the location information correctly, but broke
the type of the function). r183329 corrected the type information but
lead to the debugger interpreting the pointer parameter as the value -
the debug info describing the location needed an extra dereference.

Use a new flag in DIVariable to add the extra indirection (either by
promoting an existing DW_OP_reg (parameter passed in a register) to
DW_OP_breg + 0 or by adding DW_OP_deref to an existing DW_OP_breg + n
(parameter passed on the stack).

llvm-svn: 184368
 2013-06-19 21:55:13 +00:00
Bill Wendling
a9576dc938 Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 
llvm-svn: 184360
 2013-06-19 21:36:55 +00:00
Bill Wendling
4d82ecded8 Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 
llvm-svn: 184352
 2013-06-19 21:07:11 +00:00
Bill Wendling
1919cdf3c7 Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 
llvm-svn: 184349
 2013-06-19 20:51:24 +00:00
Matt Arsenault
fb5518e48b Move StructurizeCFG out of R600 to generic Transforms. 
Register it with PassManager

llvm-svn: 184343
 2013-06-19 20:18:24 +00:00
Vladimir Medic
10551de6bd The RenderMethod field in RegisterOperand class sets the name of the method on the target specific operand to call to add the target specific operand to an MCInst. This patch defines RenderMethod for mips RegisterOperand classes and removes redundant code from MipsAsmParser.cpp 
llvm-svn: 184292
 2013-06-19 10:14:36 +00:00
Matt Arsenault
fac93f05f8 Use GetUnderlyingObject instead of custom function 
llvm-svn: 184261
 2013-06-18 23:37:58 +00:00
Jim Grosbach
0f0c0ac8be ARM: Add optional datatype suffix to NEON mvn asm syntax. 
rdar://14194152

llvm-svn: 184244
 2013-06-18 21:49:21 +00:00
Michael Gottesman
5a5656f17d [ARMTargetLowering] ARMISD::{SUB,ADD}{C,E} second result is a boolean implying that upper bits are always 0. 
llvm-svn: 184231
 2013-06-18 20:49:45 +00:00
Michael Gottesman
dde9797dc2 Converted an overly aggressive assert to a conditional check in AddCombineTo64bitMLAL. 
Said assert assumes that ADDC will always have a glue node as its second
argument and is checked before we even know that we are actually performing the
relevant MLAL optimization. This is incorrect since on ARM we *CAN* codegen ADDC
with a use list based second argument. Thus to have both effects, I converted
the assert to a conditional check which if it fails we do not perform the
optimization.

In terms of tests I can not produce an ADDC from the IR level until I get in my
multiprecision optimization patch which is forthcoming. The tests for said patch
would cause this assert to fail implying that said tests will provide the
relevant tests.

llvm-svn: 184230
 2013-06-18 20:49:40 +00:00
Nadav Rotem
742cff8193 Fix 80 col violation. 
llvm-svn: 184228
 2013-06-18 20:41:52 +00:00
Kevin Enderby
cb41cc56c6 Change the arm assembler to support this from the v7c spec: 
"When assembling to the ARM instruction set, the .N qualifier produces
an assembler error and the .W qualifier has no effect."

In the pre-matcher handler in the asm parser the ".w" (wide) qualifier 
when in ARM mode is now discarded. And an error message is now
produced when the ".n" (narrow) qualifier is used in ARM mode.

Test cases for these were added.

rdar://14064574

llvm-svn: 184224
 2013-06-18 20:19:24 +00:00
Jack Carter
016185840e Mips ELF: Mark object file as ABI compliant 
When producing objects that are abi compliant we are 
marking neither the object file nor the assembly file
correctly and thus generate warnings. 

We need to set the EF_CPIC flag in the ELF header when
generating direct object.

Note that the warning is only generated when compiling without PIC.

When compiling with clang the warning will be suppressed by supplying:

 -Wa,-mno-shared -Wa,-call_nonpic

Also the following directive should also be added:

	.option	pic0

when compiling without PIC,  This eliminates the need for supplying:

  -mno-shared -call_nonpic

on the assembler command line.

Patch by Douglas Gilmore

llvm-svn: 184220
 2013-06-18 19:47:15 +00:00
David Blaikie
9a98240ce6 Reduce indentation. 
llvm-svn: 184213
 2013-06-18 18:03:17 +00:00
Stefanus Du Toit
aa267b3e82 Add support for encoding the HLE XACQUIRE and XRELEASE prefixes. 
For decoding, keep the current behavior of always decoding these as their REP
versions. In the future, this could be improved to recognize the cases where
these behave as XACQUIRE and XRELEASE and decode them as such.

llvm-svn: 184207
 2013-06-18 17:08:10 +00:00
Amaury de la Vieuville
0c0f005a15 ARM: fix literal load with positive offset encoding 
When using a positive offset, literal loads where encoded
as if it was negative, because:
- The sign bit was not assigned to an operand
- The addrmode_imm12 operand was not encoding the sign bit correctly

This patch also makes the assembler look at the .w/.n specifier for
loads.

llvm-svn: 184182
 2013-06-18 08:13:05 +00:00
Amaury de la Vieuville
f28bf33894 ARM: add operands pre-writeback variants when needed 
llvm-svn: 184181
 2013-06-18 08:12:51 +00:00
Amaury de la Vieuville
8d8456b196 ARM: fix thumb literal loads decoding 
This fixes two previous issues:
- Negative offsets were not correctly disassembled
- The decoded opcodes were not the right one

llvm-svn: 184180
 2013-06-18 08:03:06 +00:00
Amaury de la Vieuville
e6ed8ad5df ARM: thumb stores cannot use PC as dest register 
llvm-svn: 184179
 2013-06-18 08:02:56 +00:00
Bill Wendling
49ef14ef73 Use pointers to the MCAsmInfo and MCRegInfo. 
Someone may want to do something crazy, like replace these objects if they
change or something.

No functionality change intended.

llvm-svn: 184175
 2013-06-18 07:20:20 +00:00
Bill Wendling
6ec4332633 Remove dead prototype. 
llvm-svn: 184173
 2013-06-18 06:24:14 +00:00
Vincent Lejeune
e4a87c6317 R600: PV stores Reg id, not index 
llvm-svn: 184117
 2013-06-17 20:16:40 +00:00
Vincent Lejeune
b04cbc8058 R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen. 
Fixes rv7x0 bug in Heaven reported here:
https://bugs.freedesktop.org/show_bug.cgi?id=64257

llvm-svn: 184116
 2013-06-17 20:16:26 +00:00
David Blaikie
813e6b3974 DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs 
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.

llvm-svn: 184067
 2013-06-16 20:34:27 +00:00
David Blaikie
f3d2951503 Debug Info: Simplify Frame Index handling in DBG_VALUE Machine Instructions 
Rather than using the full power of target-specific addressing modes in
DBG_VALUEs with Frame Indicies, simply use Frame Index + Offset. This
reduces the complexity of debug info handling down to two
representations of values (reg+offset and frame index+offset) rather
than three or four.

Ideally we could ensure that frame indicies had been eliminated by the
time we reached an assembly or dwarf generation, but I haven't spent the
time to figure out where the FIs are leaking through into that & whether
there's a good place to convert them. Some FI+offset=>reg+offset
conversion is done (see PrologEpilogInserter, for example) which is
necessary for some SelectionDAG assumptions about registers, I believe,
but it might be possible to make this a more thorough conversion &
ensure there are no remaining FIs no matter how instruction selection
is performed.

llvm-svn: 184066
 2013-06-16 20:34:15 +00:00
Andrew Trick
768a74cb96 Support BufferSize on ProcResGroup for unified MOp schedulers. 
And add Sandybridge/Haswell resource buffers.

llvm-svn: 184034
 2013-06-15 04:50:06 +00:00
Andrew Trick
31eeff56c7 Update machine models. Specify buffer sizes for OOO processors. 
llvm-svn: 184033
 2013-06-15 04:50:02 +00:00