1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
Commit Graph

187988 Commits

Author SHA1 Message Date
Benjamin Kramer
b32ee4ba88 [ValueTracking] Add a basic version of isKnownNonInfinity and use it to detect more NoNaNs 2019-11-19 22:24:46 +01:00
Duncan P. N. Exon Smith
d1b42bfe87 Wrap C APIs with pragmas enforcing -Werror=strict-prototypes
Force `-Werror=strict-prototypes` so that C API tests fail to compile if
we add a non-prototype declaration.  This should help avoid regressions
like bddecba4b333f7772029b4937d2c34f9f2fda6ca was fixing.

https://reviews.llvm.org/D70285
rdar://problem/57203137
2019-11-19 13:18:43 -08:00
Philip Reames
b69bfdcade Precommit test showing oppurtunity when computing exit tests of unsimplified IR
If we partially unswitch a loop, we leave around the (and i1 X, true) or (or i1 X, false) forms.  At the moment, this inhibits SCEVs ability to compute trip counts, patch forthcoming.
2019-11-19 13:12:03 -08:00
Vedant Kumar
f90a0699e0 [CGDebugInfo] Emit subprograms for decls when AT_tail_call is understood (reland with fixes)
Currently, clang emits subprograms for declared functions when the
target debugger or DWARF standard is known to support entry values
(DW_OP_entry_value & the GNU equivalent).

Treat DW_AT_tail_call the same way to allow debuggers to follow cross-TU
tail calls.

Pre-patch debug session with a cross-TU tail call:

```
  * frame #0: 0x0000000100000fa4 main`target at b.c:4:3 [opt]
    frame #1: 0x0000000100000f99 main`main at a.c:8:10 [opt]
```

Post-patch (note that the tail-calling frame, "helper", is visible):

```
  * frame #0: 0x0000000100000fa4 main`target at b.c:4:3 [opt]
    frame #1: 0x0000000100000f80 main`helper [opt] [artificial]
    frame #2: 0x0000000100000f99 main`main at a.c:8:10 [opt]
```

This was reverted in 5b9a072c because it attached declaration
subprograms to inlinable builtin calls, which interacted badly with the
MergeICmps pass. The fix is to not attach declarations to builtins.

rdar://46577651

Differential Revision: https://reviews.llvm.org/D69743
2019-11-19 12:49:27 -08:00
Tim Northover
0e0af2537c [docs] Remove dangling parenthesis from documentation
Patch by leiteg.
2019-11-19 20:47:21 +00:00
diggerlin
b4b997378a The patch is the compiler error specific on the compile error on CMVC
SUMMARY:

CMVC has a compiler error on the
const uint64_t OffsetToRaw = is64Bit()
                                   ? toSection64(Sec)->FileOffsetToRawData
                                   : toSection32(Sec)->FileOffsetToRawData;

while  gcc  compiler do not have the problem.
I have to change the code to

  uint64_t OffsetToRaw;
  if (is64Bit())
    OffsetToRaw = toSection64(Sec)->FileOffsetToRawData;
  else
    OffsetToRaw = toSection32(Sec)->FileOffsetToRawData;

Reviewers: Sean Fertile
Subscribers: rupprecht, seiyai,hiraditya

Differential Revision: https://reviews.llvm.org/D70255
2019-11-19 15:17:56 -05:00
Vedant Kumar
1f5735e21b [DebugInfo] Describe size of spilled values in call site params
A call site parameter description of a memory operand needs to
unambiguously convey the size of the operand to prevent incorrect entry
value evaluation.

Thanks for David Stenberg for pointing this issue out!
2019-11-19 12:03:52 -08:00
Duncan P. N. Exon Smith
802dc83e3f llvm/ObjCARC: Eliminate inlined AutoreleaseRV calls
Pair up inlined AutoreleaseRV calls with their matching RetainRV or
ClaimRV.

- RetainRV cancels out AutoreleaseRV.  Delete both instructions.
- ClaimRV is a peephole for RetainRV+Release.  Delete AutoreleaseRV and
  replace ClaimRV with Release.

This avoids problems where more aggressive inlining triggers memory
regressions.

This patch is happy to skip over non-callable instructions and non-ARC
intrinsics looking for the pair.  It is likely sound to also skip over
opaque function calls, but that's harder to reason about, and it's not
relevant to the goal here: if there's an opaque function call splitting
up a pair, it's very unlikely that a handshake would have happened
dynamically without inlining.

Note that this patch also subsumes the previous logic that looked
backwards from ReleaseRV.

https://reviews.llvm.org/D70370
rdar://problem/46509586
2019-11-19 12:02:01 -08:00
Sanjay Patel
f5684993b3 [SLP] fix miscompile on min/max reductions with extra uses (PR43948) (2nd try)
The 1st attempt was reverted because it revealed an existing
bug where we could produce invalid IR (use of value before
definition). That should be fixed with:
rG39de82ecc9c2

The bug manifests as replacing a reduction operand with an undef
value.

The problem appears to be limited to cases where a min/max reduction
has extra uses of the compare operand to the select.

In the general case, we are tracking "ExternallyUsedValues" and
an "IgnoreList" of the reduction operations, but those may not apply
to the final compare+select in a min/max reduction.

For that, we use replaceAllUsesWith (RAUW) to ensure that the new
vectorized reduction values are transferred to all subsequent users.

Differential Revision: https://reviews.llvm.org/D70148
2019-11-19 14:57:35 -05:00
Evgenii Stepanov
9d3c121733 MTE: add more unchecked instructions.
Summary:
In particular, 1- and 2-byte loads and stores ignore the pointer tag
when using SP as the base register.

Reviewers: pcc, ostannard

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70341
2019-11-19 11:19:53 -08:00
Tom Stellard
49241eb38d test-release.sh: Update to fetch source from GitHub
Summary:
This also changes the test-release.sh script to build using the monorepo
layout instead of copying sub-projects into llvm/tools or llvm/projects.

Reviewers: jdoerfert, hans

Reviewed By: hans

Subscribers: hans, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70353
2019-11-19 11:13:05 -08:00
Alex Lorenz
eeeffdc6ba [ADT][Expensive checks] Create a std::random_device seed only once when shuffling before sorting
This speeds up the build of compiler-rt with an expensive checks enabled clang by an order of
1 or 2 magnitudes on my machine. I was hoping this would also fix the 'large.test' libFuzzer
timeout on the expensive checks bot on green dragon http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-expensive/,
but the fuzzer test still takes too long to compile because of other IR/MIR verification inefficiencies.

Differential Revision: https://reviews.llvm.org/D70288
2019-11-19 11:07:58 -08:00
David Green
d4ff6cb651 [ARM] MVE interleaving load and stores.
Now that we have the intrinsics, we can add VLD2/4 and VST2/4 lowering
for MVE. This works the same way as Neon, recognising the load/shuffles
combination and converting them into intrinsics in a pre-isel pass,
which just calls getMaxSupportedInterleaveFactor, lowerInterleavedLoad
and lowerInterleavedStore.

The main difference to Neon is that we do not have a VLD3 instruction.
Otherwise most of the code works very similarly, with just some minor
differences in the form of the intrinsics to work around. VLD3 is
disabled by making isLegalInterleavedAccessType return false for those
cases.

We may need some other future adjustments, such as VLD4 take up half the
available registers so should maybe cost more. This patch should get the
basics in though.

Differential Revision: https://reviews.llvm.org/D69392
2019-11-19 18:37:30 +00:00
David Green
309c4626ef [ARM] Add and update a lot of VLDn tests. NFC 2019-11-19 18:37:30 +00:00
diggerlin
9bd38dc12c implement printing out raw section data of xcoff objectfile for llvm-objdump
SUMMARY:
implement printing out raw section data of xcoff objectfile for llvm-objdump
and option -D --disassemble-all option for llvm-objdump

Reviewers: Sean Fertile
Subscribers: rupprecht, seiyai,hiraditya

Differential Revision: https://reviews.llvm.org/D70255
2019-11-19 13:31:00 -05:00
Joel E. Denny
15ec0cb41e [FileCheck] Use lit's internal shell for the test suite
An advantage is that there are less portability concerns when writing
tests.  For example, `-u` is not supported by all implementations of
`env`, but lit's internal shell provides its own `env` that supports
`-u`.

A disadvantage is that some shell constructs, such as parentheses, are
not supported, but FileCheck's test suite currently doesn't require
such constructs.

For comparison, lit configures its test suite in the same manner.  See
`llvm/utils/lit/tests/lit.cfg`.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D70278
2019-11-19 12:08:54 -05:00
LLVM GN Syncbot
298b2eff0e gn build: Merge 7fe9435dc88 2019-11-19 16:34:22 +00:00
Matt Arsenault
00e1bbce35 Work on cleaning up denormal mode handling
Cleanup handling of the denormal-fp-math attribute. Consolidate places
checking the allowed names in one place.

This is in preparation for introducing FP type specific variants of
the denormal-fp-mode attribute. AMDGPU will switch to using this in
place of the current hacky use of subtarget features for the denormal
mode.

Introduce a new header for dealing with FP modes. The constrained
intrinsic classes define related enums that should also be moved into
this header for uses in other contexts.

The verifier could use a check to make sure the denorm-fp-mode
attribute is sane, but there currently isn't one.

Currently, DAGCombiner incorrectly asssumes non-IEEE behavior by
default in the one current user. Clang must be taught to start
emitting this attribute by default to avoid regressions when this is
switched to assume ieee behavior if the attribute isn't present.
2019-11-19 22:01:14 +05:30
Pavel Labath
8d1cc55d9b [cmake] Disable GCC 9's -Winit-list-lifetime warning in ArrayRef
Summary:
This is a new warning which fires when one stores a reference to the
initializer_list contents in a way which may outlive the
initializer_list which it came from. In llvm this warning is triggered
whenever someone uses the initializer_list ArrayRef constructor.

This is indeed a dangerous thing to do (I myself was bitten by that at
least once), but it is not more dangerous than calling other ArrayRef
constructors with temporary objects -- something which we are used to
and have accepted as a tradeoff for ArrayRef's efficiency.

Currently, this warnings generates so much output that it completely
obscures any actionable warnings, so this patch disables it.

Reviewers: rnk, aaron.ballman

Subscribers: mgorny, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70122
2019-11-19 17:26:57 +01:00
jasonliu
12f86d642d [AIX][XCOFF] Write Function descriptors and TOC base to data section
This patch implements writing function descriptors and TOC base into
data section, and also add function descriptors(both csect and label)
and TOC base symbols to the symbol table.
2019-11-19 16:11:00 +00:00
Sanjay Patel
a4afe9d56f [SLP] fix insertion point for min/max reduction
As discussed in D70148 (and caused a revert of the original commit):
if we insert at the select, then we can produce invalid IR because
the replacement for the compare may have uses before the select.
2019-11-19 10:50:10 -05:00
LLVM GN Syncbot
3ae6437414 gn build: Merge 765b1250f68 2019-11-19 15:33:25 +00:00
David Bozier
1dbe33cab9 Fixup AVR tests to reflect changes in addend format in llvm-objdump
Summary: Changes to llvm-objdump made in D69997

Reviewers: thakis, jhenderson, grimar

Reviewed By: thakis

Subscribers: dylanmckay, Jim, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70438
2019-11-19 15:32:58 +00:00
Sanjay Patel
7da0f4eb10 [SLP] add test for reduction miscompile; NFC
See D70148 for discussion.
2019-11-19 10:24:32 -05:00
Simon Tatham
7935cf1c34 [ARM,MVE] Add intrinsics for scalar shifts.
This fills in the small family of MVE intrinsics that have nothing to
do with vectors: they implement bit-shift operations on 32- or 64-bit
values held in one or two general-purpose registers. Most of these
shift operations saturate if shifting left, and round to nearest if
shifting right, although LSLL and ASRL behave like ordinary shifts.

When these instructions take a variable shift count in a register,
they pay attention to its sign, so that (for example) LSLL or UQRSHLL
will shift left if given a positive number but right if given a
negative one. That makes even LSLL and ASRL different enough from
standard LLVM IR shift semantics that I couldn't see any better
alternative than to simply model the whole family as a set of
MVE-specific IR intrinsics.

(The //immediate// forms of LSLL and ASRL, on the other hand, do
behave exactly like a standard IR shift of a 64-bit value. In fact,
those forms don't have ACLE intrinsics defined at all, because you can
just write an ordinary C shift operation if you want one of those.)

The 64-bit shifts have to be instruction-selected in C++, because they
deliver two output values. But the 32-bit ones are simple enough that
I could write a DAG isel pattern directly into each Instruction
record.

Reviewers: ostannard, MarkMurrayARM, dmgreen

Reviewed By: dmgreen

Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D70319
2019-11-19 14:47:29 +00:00
Matt Arsenault
3b2b582539 AMDGPU: Refactor treatment of denormal mode
Start moving towards treating this as a property of the calling
convention, and not the subtarget. The default denormal mode should
not be part of the subtarget, and be moved into a separate function
attribute.

This patch is still NFC. The denormal mode remains as a subtarget
feature for now, but make the necessary changes to switch to using an
attribute.
2019-11-19 19:55:43 +05:30
Matt Arsenault
907a06be36 AMDGPU: Be explicit about denormal mode in MIR tests
Start checking the machine function in GlobalISel instead of the
target directly.

This temporarily breaks fcanonicalize selection in GlobalISel.
2019-11-19 19:55:43 +05:30
Matt Arsenault
78c8c056b5 DAG: Add function context to isFMAFasterThanFMulAndFAdd
AMDGPU needs to know the FP mode for the function to answer this
correctly when this is removed from the subtarget.

AArch64 had to make this more complicated by using this from an IR
hook, so add an IR typed overload.
2019-11-19 19:25:26 +05:30
Raphael Isemann
3598ed7aee Fix modules build by adding missing includes 2019-11-19 14:37:18 +01:00
dfukalov
2fc96e575d [AMDGPU] Tune inlining parameters for AMDGPU target (part 2)
Summary:
Most of IR instructions got better code size estimations after commit 47a5c36b.
So default parameters values should be updated to improve inlining and
unrolling for the target.

Reviewers: rampitec, arsenm

Reviewed By: rampitec

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, zzheng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70391
2019-11-19 16:33:16 +03:00
Roman Lebedev
005447e1cc [NFC][X86] Fixup comment in CodeGen/X86/cmov.ll
As noted in post-commit review for
https://reviews.llvm.org/D59035#inline-631659
2019-11-19 16:24:07 +03:00
Simon Pilgrim
83b9d3ef52 [ARM] Regenerate vector lane store tests 2019-11-19 13:18:44 +00:00
Simon Pilgrim
79da5d67c0 [PowerPC] Regenerate vsx_insert_extract_le.ll tests 2019-11-19 13:18:44 +00:00
evgeny
0736e026a7 [ThinLTO] Simplify code. NFC 2019-11-19 15:51:25 +03:00
David Bozier
02d3efaf7f [llvm-objdump] Print relocation addends in hexadecimal
Summary: Matches GNU objdump. Makes debugging easier for me as I'm working out addresses from symbol+addend, so it would be good to be calculating in a single format.

Reviewers: MaskRay, grimar, jhenderson, bd1976llvm

Reviewed By: jhenderson

Subscribers: sdardis, jrtc27, atanasyan, rupprecht, seiya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69997
2019-11-19 12:27:18 +00:00
Simon Pilgrim
46989d6a40 [X86][SSE] Remove XFormVExtractWithShuffleIntoLoad to prevent legalization infinite loops (PR43971)
As detailed in PR43971/D70267, the use of XFormVExtractWithShuffleIntoLoad causes issues where we end up in infinite loops of extract(targetshuffle(vecload)) -> extract(shuffle(vecload)) -> extract(vecload) -> extract(targetshuffle(vecload)), there are just too many legalization checks at every stage that we can't guarantee that extract(shuffle(vecload)) -> scalarload can occur.

At the moment we see a number of minor regressions as we don't fold extract(shuffle(vecload)) -> scalarload before legal ops, these can be addressed in future patches and extension of X86ISelLowering's combineExtractWithShuffle.
2019-11-19 11:55:44 +00:00
Thomas Preud'homme
646f60afdf Fix PR44001: assert failure in getFunctionLocalOffsetAfterInsn
Summary:
Assert in getFunctionLocalOffsetAfterInsn() fails when processing a call
MachineInstr inside a bundle and compiling with debug info. This is
because labels are added by DwarfDebug::beginInstruction() which is
called for each top-level MI by EmitFunctionBody()'s for-loop iteration
but constructCallSiteEntryDIEs() which calls
getFunctionLocalOffsetAfterInsn() iterates over all MIs.

This commit modifies constructCallSiteEntryDIEs() to get the associated
bundle MI for call MIs inside a bundle and use that to when calling
getFunctionLocalOffsetAfterInsn() and getLabelAfterInsn(). It also skips
loop iterations for bundle MIs since the loop statements are concerned
with debug info for each physical instructions and bundles represent a
group of instructions. It also fix the comment about PCAddr since the
code is getting the return address and not the call address.

Reviewers: dstenb, vsk, aprantl, djtodoro, dblaikie, NikolaPrica

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70293
2019-11-19 11:23:11 +00:00
Simon Atanasyan
ba21ea0d08 [mips] Joint MipsMemSimmXXXAsmOperand into the single template class. NFC 2019-11-19 13:58:28 +03:00
LLVM GN Syncbot
8d49aea2ea gn build: Merge e8a4c74f115 2019-11-19 10:34:24 +00:00
Evgeniy Brevnov
dfb6fb4976 [DependenceAnalysis] Dependecies for loads marked with "ivnariant.load" should not be shared with general accesses. Fix for https://bugs.llvm.org/show_bug.cgi?id=42151
Summary:
Dependence anlysis has a mechanism to cache results. Thus for particular memory access the cache keep track of side effects in basic blocks. The problem is that for invariant loads dependepce analysis legally ignores many dependencies due to a special semantic rules for such loads. But later results calculated for invariant load retrived from the cache for general case acceses. As a result we have wrong dependence information causing GVN to do illegal transformation. Fixes, T42151.

Proposed solution is to disable caching of invariant loads. I think such loads a pretty rare and it doesn't make sense to extend caching mechanism for them.

Reviewers: reames, chandlerc, skatkov, morisset, jdoerfert

Reviewed By: reames

Subscribers: hiraditya, test, jdoerfert, lebedev.ri, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64405
2019-11-19 17:30:02 +07:00
evgeny
fa92ba961c [ThinLTO] Make ValueInfo::operator bool() explicit
Differential revision: https://reviews.llvm.org/D70383
2019-11-19 12:46:09 +03:00
LLVM GN Syncbot
0f5b4869fb gn build: Merge c0fc29c4684 2019-11-19 09:55:01 +00:00
LLVM GN Syncbot
95b601a26f gn build: Merge 39285a0f02c 2019-11-19 09:55:01 +00:00
Sven van Haastregt
b2a53de233 [kate] Add various missing keywords
Patch by Pedro Olsen Ferreira.
2019-11-19 09:54:07 +00:00
Nico Weber
fd27d21be7 Revert "gn build: (manually) try to merge 1689ad27af"
This reverts commit e4ec2ecf6d4768d681a89263c0a4d29a7b7761ad.
1689ad27af was reverted as well.
2019-11-19 04:40:10 -05:00
Pavel Labath
ed1ed38a5b Add streaming/equality operators to DWARFAddressRange/DWARFLocationExpression
The main motivation for this is being able to write simpler assertions
and get better error messages in unit tests.

Split off from D70394.
2019-11-19 10:34:30 +01:00
Pavel Labath
53a4d76970 Add operator<< for object::SectionedAddress
The main motivation for this is better failure messages in unit tests.

Split off from D70394.
2019-11-19 10:34:30 +01:00
czhengsz
151a0b69c7 [APInt] add wrap support for setBits and getBitsSet
Add two new interfaces getBitsSet and getBitsSetWithWrap

Reviewed by: lebedev.ri, craig.topper

Differential Revision: https://reviews.llvm.org/D69032
2019-11-19 03:57:48 -05:00
Sam Parker
6a6837086c [ARM][MVE] Enable narrow vectors for tail pred
Remove the restriction, from the mve tail predication pass, that the
all masked vectors instructions need to be 128-bits. This allows us
to supported extending loads and truncating stores.

Differential Revision: https://reviews.llvm.org/D69946
2019-11-19 08:51:12 +00:00
Evgeniy Brevnov
ebd164db73 [NFC] Test commit. Please ignore.
As a test commit I fixed a misspelling in one of comments in SLP
vectorizer.
2019-11-19 15:41:57 +07:00