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49977 Commits

Author SHA1 Message Date
Owen Anderson
d3151e11e8 Start stubbing out MCModule and MCAtom, which provide an API for accessing the rich disassembly of a complete object or executable. 
These are very much a work in progress, and not really useful yet.

llvm-svn: 140345
 2011-09-22 22:32:22 +00:00
Jakob Stoklund Olesen
dedb558e4d Constrain register classes instead of emitting copies. 
Sometimes register class constraints are trivial, like GR32->GR32_NOSP,
or GPR->rGPR.  Teach InstrEmitter to simply constrain the virtual
register instead of emitting a copy in these cases.

Normally, these copies are handled by the coalescer.  This saves some
coalescer work.

llvm-svn: 140340
 2011-09-22 21:39:34 +00:00
Jakob Stoklund Olesen
1d3105c3d3 Add a MinNumRegs argument to MRI::constrainRegClass(). 
The function will refuse to use a register class with fewer registers
than MinNumRegs.  This can be used by clients to avoid accidentally
increase register pressure too much.

The default value of MinNumRegs=0 doesn't affect how constrainRegClass()
works.

llvm-svn: 140339
 2011-09-22 21:39:31 +00:00
Duncan Sands
1da590b589 Synthesize SSE3/AVX 128 bit horizontal add/sub instructions from 
floating point add/sub of appropriate shuffle vectors.  Does not
synthesize the 256 bit AVX versions because they work differently.

llvm-svn: 140332
 2011-09-22 20:15:48 +00:00
Eli Friedman
6e15091fc6 PR10987: add a missed safety check to isSafePHIToSpeculate in scalarrepl. 
llvm-svn: 140327
 2011-09-22 18:56:30 +00:00
Akira Hatanaka
82aaeed7f4 Print parentheses in next line. 
llvm-svn: 140325
 2011-09-22 18:29:29 +00:00
Akira Hatanaka
7bba6afecf Change subreg index of AFPR64 from sub_fpeven to sub_32 per Jakob's comment. 
llvm-svn: 140324
 2011-09-22 18:24:21 +00:00
Akira Hatanaka
eaf1e32694 Define a new sub-register index sub_32 for accessing the 32-bit sub-register of 
a 64-bit integer register. Move the subreg index definitions to the beginning
of the file.

llvm-svn: 140319
 2011-09-22 17:57:32 +00:00
Bill Wendling
4a26d03528 Use the C personality function instead of the C++ personality function. 
llvm-svn: 140318
 2011-09-22 17:56:40 +00:00
Akira Hatanaka
329b07db41 Print three closing parentheses when Kind is either VK_Mips_GPOFF_HI or 
VK_Mips_GPOFF_LO.

llvm-svn: 140316
 2011-09-22 17:44:37 +00:00
Akira Hatanaka
96122b7f72 Add F31 to the set of callee-saved registers. 
llvm-svn: 140315
 2011-09-22 17:35:03 +00:00
Akira Hatanaka
6b99d9b0f3 Fix typo. 
llvm-svn: 140313
 2011-09-22 17:26:58 +00:00
Justin Holewinski
a43c9dc50c PTX: Remove physical register defs 
llvm-svn: 140310
 2011-09-22 16:45:48 +00:00
Justin Holewinski
04f4046d9f PTX: Use .param space for device function return values on SM 2.0+, and attempt 
to fix up parameter passing on SM < 2.0

llvm-svn: 140309
 2011-09-22 16:45:46 +00:00
Justin Holewinski
987b8f7a69 PTX: Fix style issues 
llvm-svn: 140308
 2011-09-22 16:45:43 +00:00
Justin Holewinski
815227205d PTX: Fixup codegen to handle emission of virtual registers. 
llvm-svn: 140307
 2011-09-22 16:45:40 +00:00
Justin Holewinski
1dd4cf37f8 PTX: Customize codegen passes in backend 
llvm-svn: 140306
 2011-09-22 16:45:37 +00:00
Justin Holewinski
fee8e64e4d PTX: Add new PTX-specific register allocator that keeps virtual registers 
instead of allocating physical registers.

This is part of a work-in-progress overhaul of the PTX register allocation scheme.

llvm-svn: 140305
 2011-09-22 16:45:33 +00:00
Craig Topper
95f048d1ff Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960 
llvm-svn: 140299
 2011-09-22 07:01:50 +00:00
Akira Hatanaka
12218a1192 Add definition of 64-bit floating registers used for Mips64. 
llvm-svn: 140297
 2011-09-22 03:48:47 +00:00
Benjamin Kramer
978ef840ac The SSE version differences for fmin/fmax are more involved than I thought. 
- x87: no min or max.
- SSE1: min/max for single precision scalars and vectors.
- SSE2: min/max for single and double precision scalars and vectors.
- AVX: as SSE2, but also supports the wider ymm vectors. (this is covered by the isTypeLegal check)

llvm-svn: 140296
 2011-09-22 03:27:22 +00:00
Akira Hatanaka
d34925f313 Add enums and functions for symbols Mips64 uses. 
llvm-svn: 140295
 2011-09-22 03:09:07 +00:00
Benjamin Kramer
5844bacf0a X86: Don't form min/max nodes if the target is missing SSE. 
llvm-svn: 140294
 2011-09-22 03:01:42 +00:00
Akira Hatanaka
65c0724c19 Mips64 aligns stack on 16-byte boundary. 
llvm-svn: 140292
 2011-09-22 02:53:37 +00:00
Akira Hatanaka
60cd2b0c2f Remove unnecessary condition check. 
llvm-svn: 140291
 2011-09-22 02:41:29 +00:00
Owen Anderson
22ab29756b Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused. 
llvm-svn: 140284
 2011-09-21 23:53:44 +00:00
Owen Anderson
7b134fe54c Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123. 
llvm-svn: 140283
 2011-09-21 23:44:46 +00:00
Devang Patel
5d43ab8434 Do not unnecessarily use AT_specification DIE because it does not add any value. 
Few weeks ago, llvm completely inverted the debug info graph. Earlier each debug info node used to keep track of its compile unit, now compile unit keeps track of important nodes. One impact of this change is that the global variable's do not have any context, which should be checked before deciding to use AT_specification DIE.

llvm-svn: 140282
 2011-09-21 23:41:11 +00:00
Galina Kistanova
5d64adbe43 Fix for DbgInfoPrinter.cpp:174:12: warning: ‘LineNo’ may be used uninitialized in this function. 
llvm-svn: 140281
 2011-09-21 23:34:23 +00:00
Bill Wendling
97f5bfd1a3 The last verification check for the new EH model. 
This makes sure that the unwind destination of an invoke is a landing pad.

llvm-svn: 140280
 2011-09-21 22:57:02 +00:00
Bill Wendling
1038de0df8 Attempt to update the shadow stack GC pass to the new EH model. 
This inserts a cleanup landingpad instruction and a resume to mimic the old
unwind instruction.

llvm-svn: 140277
 2011-09-21 22:14:28 +00:00
Benjamin Kramer
8b12bfc4ec X86Disassembler: if verbose logging is going to nulls(), disable logging completely. 
Otherwise we'll spend a ridiculous amount of time pretty printing debug output and then discarding it.

llvm-svn: 140276
 2011-09-21 21:47:35 +00:00
Jim Grosbach
74679928e9 Tidy up. Whitepsace. 
llvm-svn: 140275
 2011-09-21 21:36:53 +00:00
Wesley Peck
10002dcc07 Fix some simple copy-paste errors in MBlaze ASM Parser and Makefile. 
patch contributed by Jia Liu!

llvm-svn: 140273
 2011-09-21 19:23:46 +00:00
Owen Anderson
220db2953c These do not need to be conditional on the presence of CommentStream, as they have a fallback path now. 
llvm-svn: 140267
 2011-09-21 17:58:45 +00:00
Akira Hatanaka
8c3fbb9a71 Undo a change made in r140254. 
MipsArchVersion needs to be initialized to Mips32.

llvm-svn: 140261
 2011-09-21 17:31:45 +00:00
Benjamin Kramer
ff31737153 DWARF: avoid unnecessary map lookups. 
llvm-svn: 140260
 2011-09-21 17:31:42 +00:00
Nadav Rotem
71bd67ac2e fix comment 
llvm-svn: 140258
 2011-09-21 17:14:40 +00:00
Akira Hatanaka
c9f510b4e9 MipsArchVersion does not need to be in the initialization list and MipsABI 
should be initialized to UnknownABI.

llvm-svn: 140254
 2011-09-21 16:41:43 +00:00
Nadav Rotem
af5643de3c [VECTOR-SELECT] Address one of the bugs in pr10902. 
Vector SetCC result types need to be type-legalized.
This code worked before because scalar result types are known to be legal.

llvm-svn: 140249
 2011-09-21 14:34:38 +00:00
Nadav Rotem
8fc9d777a3 Insert a sanity check on the combining of x86 truncing-store nodes. This comes to replace the problematic check that was removed in r139995. 
llvm-svn: 140246
 2011-09-21 08:45:10 +00:00
Richard Trieu
a675de9fac Change: 
assert(!"error message");

To:

  assert(0 && "error message");

which is more consistant across the code base.

llvm-svn: 140234
 2011-09-21 03:09:09 +00:00
Akira Hatanaka
88ce0f7440 Add a base class for Mips TargetMachines and add Mips64 TargetMachines. 
llvm-svn: 140233
 2011-09-21 03:00:58 +00:00
Akira Hatanaka
a936c212fa Set ABI if it hasn't been set on the command line. 
Check if architecture & ABI combination is valid.

llvm-svn: 140230
 2011-09-21 02:45:29 +00:00
Akira Hatanaka
31b9daf57e Fix typo. 
llvm-svn: 140229
 2011-09-21 02:24:25 +00:00
Andrew Trick
c94573ded6 Lower ARM adds/subs to add/sub after adding optional CPSR operand. 
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.

llvm-svn: 140228
 2011-09-21 02:20:46 +00:00
Andrew Trick
5b514628ed whitespace 
llvm-svn: 140227
 2011-09-21 02:17:37 +00:00
Owen Anderson
fbec62c99e In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on. 
llvm-svn: 140217
 2011-09-21 00:25:23 +00:00
Akira Hatanaka
eb3e16d39f Change the names of functions isMips* to hasMips*. 
llvm-svn: 140214
 2011-09-20 23:53:09 +00:00
Eli Friedman
2599a202e2 Make sure IPSCCP never marks a tracked call as overdefined in SCCPSolver::ResolvedUndefsIn. If we do, we can end up in a situation where a function is resolved to return a constant, but the caller is marked overdefined, which confuses the code later. 
<rdar://problem/9956541> (again).

llvm-svn: 140210
 2011-09-20 23:28:51 +00:00