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48362 Commits

Author SHA1 Message Date
Akira Hatanaka
b4db39fa83 Use descriptive variable names. 
llvm-svn: 135514
 2011-07-19 20:11:17 +00:00
Jim Grosbach
9debba28ed ARM assembly parsing for MOV (register). 
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.

llvm-svn: 135513
 2011-07-19 20:10:31 +00:00
Jim Grosbach
7e61a1ecf2 Tidy up. 
llvm-svn: 135507
 2011-07-19 19:47:11 +00:00
Jim Grosbach
8ebe7d700a Tighten conditional for 'mov' cc_out. 
Make sure we only clobber the cc_out operand if it is indeed a default
non-setting operand.

llvm-svn: 135506
 2011-07-19 19:45:44 +00:00
Devang Patel
5a4bb57ec5 Reapply r135457. This needs llvm-gcc change, that I forgot to check-in yesterday. 
llvm-svn: 135504
 2011-07-19 19:41:54 +00:00
Jim Grosbach
294b83e3e2 ARM assembly parsing for MOV (immediate). 
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.

llvm-svn: 135500
 2011-07-19 19:13:28 +00:00
Jim Grosbach
14e26dd644 Remove unused code. 
cc_out and pred operands are added during parsing via custom C++ now.

llvm-svn: 135497
 2011-07-19 18:32:48 +00:00
Akira Hatanaka
19c16a84ff Fix comments. 
llvm-svn: 135496
 2011-07-19 18:19:40 +00:00
Akira Hatanaka
f59cbeec14 Remove redundant instructions. 
- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
  instruction being expanded, instead of masking it in thisMBB. 
- Remove redundant Or in EmitAtomicCmpSwap. 

llvm-svn: 135495
 2011-07-19 18:14:26 +00:00
Akira Hatanaka
57d207bc7b Separate code that modifies control flow from code that adds instruction to 
basic blocks.

llvm-svn: 135490
 2011-07-19 17:09:53 +00:00
Jim Grosbach
31cda4ed6d ARM range checking for so_imm operands in assembly parsing. 
llvm-svn: 135489
 2011-07-19 16:50:30 +00:00
Bob Wilson
7c9092c9aa Revert "Make a provision to encode inline location in a variable. This will enable dwarf writer to easily distinguish between two instances of a inlined variable in one basic block." 
This reverts commit 9fec5e346efdf744b151ae6604f912908315fa7a.

llvm-svn: 135486
 2011-07-19 16:32:50 +00:00
Jay Foad
6d007bef3c Convert ConstantFoldGetElementPtr to use ArrayRef. 
llvm-svn: 135483
 2011-07-19 15:30:30 +00:00
Jay Foad
bbbf29aab7 Convert SimplifyGEPInst to use ArrayRef. 
llvm-svn: 135482
 2011-07-19 15:07:52 +00:00
Jay Foad
83a0e1fa99 Convert gep_type_begin and gep_type_end to use ArrayRef. 
llvm-svn: 135481
 2011-07-19 14:42:50 +00:00
Jay Foad
0974b71f17 Convert TargetData::getIndexedOffset to use ArrayRef. 
llvm-svn: 135478
 2011-07-19 14:01:37 +00:00
Jay Foad
ae5894c5cc Use ArrayRef in ConstantFoldInstOperands and ConstantFoldCall. 
llvm-svn: 135477
 2011-07-19 13:32:40 +00:00
Richard Osborne
b469141419 Add intrinsics for the zext / sext instructions. 
llvm-svn: 135476
 2011-07-19 13:28:50 +00:00
Richard Osborne
50303e0d38 Add intrinsics for the testct, testwct instructions. 
llvm-svn: 135475
 2011-07-19 13:00:40 +00:00
Richard Osborne
409c0d7768 Add intrinsics for the peek and endin instructions. 
llvm-svn: 135474
 2011-07-19 12:50:25 +00:00
Evan Cheng
bfc0cac54d Introduce MCCodeGenInfo, which keeps information that can affect codegen 
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.

llvm-svn: 135468
 2011-07-19 06:37:02 +00:00
Akira Hatanaka
ad3687eb3a Make EmitAtomic functions return the correct MachineBasicBlocks so that 
ExpandISelPseudos::runOnMachineFunction does not visit instructions that have
just been added.

llvm-svn: 135465
 2011-07-19 03:42:13 +00:00
Akira Hatanaka
55b8d79a52 Do not insert instructions in reverse order. 
llvm-svn: 135464
 2011-07-19 03:14:58 +00:00
Devang Patel
e50d45c876 Make a provision to encode inline location in a variable. This will enable dwarf writer to easily distinguish between two instances of a inlined variable in one basic block. 
llvm-svn: 135457
 2011-07-19 01:03:32 +00:00
Devang Patel
72886ba8d8 Revert r135423. 
llvm-svn: 135454
 2011-07-19 00:28:24 +00:00
Bill Wendling
cd5cb5b44e Micro-opt: Only emit compact unwind if there is a compact unwind encoding to emit. 
llvm-svn: 135452
 2011-07-19 00:09:25 +00:00
Bill Wendling
8dd021da20 Use the CompactUnwindEncoding from the Frame, if it's defined. 
llvm-svn: 135451
 2011-07-19 00:06:12 +00:00
Bill Wendling
71a83a3b30 Add a frame with the compact unwind encoding if it exists. 
llvm-svn: 135450
 2011-07-19 00:02:51 +00:00
Bill Wendling
6211e2602f Add a method to set compact unwind encoding information in a frame. 
llvm-svn: 135449
 2011-07-19 00:01:42 +00:00
Bill Wendling
b1d5a0798a Rename CompactEncoding to CompactUnwindEncoding. 
llvm-svn: 135448
 2011-07-19 00:00:58 +00:00
Sean Callanan
b5cc61ce9a Fixed a bug where the MC subtarget information 
wasn't being initialized by the enhanced disassembler,
leading to assertion failures. 

llvm-svn: 135447
 2011-07-19 00:00:41 +00:00
Bill Wendling
203796ee7a Move the compact encoding from the target-specific library to the code-gen 
library.

llvm-svn: 135443
 2011-07-18 23:38:40 +00:00
Owen Anderson
27021374f8 Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having multiple instructions with the same encoding. This resolves another conflict when bringing up the new-style disassembler. 
llvm-svn: 135442
 2011-07-18 23:25:34 +00:00
Evan Cheng
5ad7d33696 Eliminate TargetAsmInfo::getCompactUnwindEncoding. This get rid of the 
use of TargetFrameLowering in TargetAsmInfo.

llvm-svn: 135439
 2011-07-18 22:32:12 +00:00
Evan Cheng
10c6820ff4 Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for 
better location welcome).

llvm-svn: 135438
 2011-07-18 22:29:13 +00:00
Owen Anderson
b32dac81e0 Mark the Darwin assembler workout as isCodeGenOnly, so that it doesn't cause decoding conflicts in the new-style disassembler. 
llvm-svn: 135434
 2011-07-18 22:14:02 +00:00
Jeffrey Yasskin
2e0f2a0985 Add APInt(numBits, ArrayRef<uint64_t> bigVal) constructor to prevent future ambiguity 
errors like the one corrected by r135261.  Migrate all LLVM callers of the old
constructor to the new one.

llvm-svn: 135431
 2011-07-18 21:45:40 +00:00
Andrew Trick
ff306f7c8b Compiler warning. 
llvm-svn: 135426
 2011-07-18 21:15:03 +00:00
Evan Cheng
561d71ce7b Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down 
to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.

llvm-svn: 135424
 2011-07-18 20:57:22 +00:00
Devang Patel
389cb9d8c6 During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases. 
[take 2]

llvm-svn: 135423
 2011-07-18 20:55:23 +00:00
Andrew Trick
ba37b6516a indvars: LinearFunctionTestReplace for non-canonical IVs. 
For -disable-iv-rewrite, perform LFTR without generating a new
"canonical" induction variable. Instead find the "best" existing
induction variable for use in the loop exit test and compute the final
value of that IV for use in the new loop exit test. In short,
convert to a simple eq/ne exit test as long as it's cheap to do so.

llvm-svn: 135420
 2011-07-18 20:32:31 +00:00
Akira Hatanaka
52263f51f1 Do not treat atomic.load.sub differently than other atomic binary intrinsics. 
llvm-svn: 135418
 2011-07-18 19:58:59 +00:00
Akira Hatanaka
79f38f0ae7 Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from 
moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.

llvm-svn: 135415
 2011-07-18 18:52:12 +00:00
Owen Anderson
aadc53ca80 Re-apply r135319 with a fix for the constant island pass. 
Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode.  Update the ARM disassembler for this change.

llvm-svn: 135414
 2011-07-18 18:50:52 +00:00
Jakob Stoklund Olesen
89e84069d2 Fix a crash when building 177.mesa for armv6. 
When splitting a live range immediately before an LDR_POST instruction
that redefines the address register, make sure to use the correct value
number in leaveIntvBefore.

We need the value number entering the instruction.

<rdar://problem/9793765>

llvm-svn: 135413
 2011-07-18 18:47:13 +00:00
Andrew Trick
40113d052b indvars: Added verification that LFTR and other indvars goodness does 
not interfere with BackedgeTakenCount computation.

llvm-svn: 135412
 2011-07-18 18:44:20 +00:00
Andrew Trick
111d0bc134 indvars: Added isHighCostExpansion. Avoid generating extra ops in the 
preheader for the sole purpose of LFTR, since LFTR itself is usually not
a clear optimization.

llvm-svn: 135409
 2011-07-18 18:21:35 +00:00
Bruno Cardoso Lopes
bdf75dfa28 Be more smart with VCVTSS2SD. Also place the patterns close to the 
definitions.

llvm-svn: 135407
 2011-07-18 18:11:25 +00:00
Bruno Cardoso Lopes
da90f383ab Add AVX 128-bit sqrt versions 
llvm-svn: 135404
 2011-07-18 17:51:40 +00:00
Akira Hatanaka
d5690b20d3 Change destination register operands of SC instructions so that unique 
virtual registers are used. 

llvm-svn: 135403
 2011-07-18 17:44:27 +00:00