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b5fde80c0e
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2 Commits

Author SHA1 Message Date
Alex Bradbury
b5fde80c0e [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td 
For now, only add instruction definitions for basic ALU operations. Our 
initial target is a working MC layer rather than codegen, so appropriate 
SelectionDAG patterns will come later.

Differential Revision: https://reviews.llvm.org/D23561

llvm-svn: 285769
 2016-11-01 23:40:28 +00:00
Alex Bradbury
4b9563cf55 [RISCV] Add stub backend 
This contains just enough for lib/Target/RISCV to compile. Notably a basic 
RISCVTargetMachine and RISCVTargetInfo. At this point you can attempt llc 
-march=riscv32 myinput.ll and will find it fails due to the lack of 
MCAsmInfo.

See http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748.html for 
further discussion

Differential Revision: https://reviews.llvm.org/D23560

llvm-svn: 285712
 2016-11-01 17:27:54 +00:00