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Commit Graph

20013 Commits

Author SHA1 Message Date
Andrew Trick
b79ae09045 LFTR improvement to avoid truncation.
This is a reimplemntation of the patch originally in r186107.

llvm-svn: 186215
2013-07-12 22:08:48 +00:00
Benjamin Kramer
dfbb134032 R600: Reapply testcase from r186178, the big endian issue should be fixed by r186196.
llvm-svn: 186209
2013-07-12 21:54:43 +00:00
Rafael Espindola
49171a7db7 Change archive-update.test to create a new file on the fly.
llvm-svn: 186206
2013-07-12 21:17:17 +00:00
Rafael Espindola
6cc9c76d58 Rename directory to avoid problems on windows.
llvm-svn: 186202
2013-07-12 20:53:23 +00:00
Rafael Espindola
6c3ac6c001 Change llvm-ar to use lib/Object.
This fixes two bugs is lib/Object that the use in llvm-ar found:
* In OS X created archives, the name can be padded with nulls. Strip them.
* In the constructor, remember the first non special member and use that in
  begin_children. This makes sure we skip all special members, not just the
  first one.

The change to llvm-ar itself consist of
* Using lib/Object for reading archives instead of ArchiveReader.cpp.
* Writing the modified archive directly, instead of creating an in memory
  representation.

The old Archive library was way more general than what is needed, as can
be seen by the diffstat of this patch.

Having llvm-ar using lib/Object now opens the way for creating regular symbol
tables for both native objects and bitcode files so that we can use those
archives for LTO.

llvm-svn: 186197
2013-07-12 20:21:39 +00:00
Rafael Espindola
b62b63af64 Add a test for llvm-ar's u option.
llvm-svn: 186192
2013-07-12 19:34:24 +00:00
Tom Stellard
7645224e44 R600: Remove the fpconst64.ll test which was failing on non-x86 buildbots
I'm guessing the failure had something to do with the double precision
floating point constant used in the test.

llvm-svn: 186191
2013-07-12 19:29:54 +00:00
Arnold Schwaighofer
acadd7e840 X86 cost model: Add cost for vectorized gather/scather
radar://14351991

llvm-svn: 186189
2013-07-12 19:16:07 +00:00
Arnold Schwaighofer
17fdc6e770 ARM cost model: Add cost for gather/scather
Fixes a 35% degradation compared to unvectorized code in
MiBench/automotive-susan and an equally serious regression on a private
image processing benchmark.

radar://14351991

llvm-svn: 186188
2013-07-12 19:16:04 +00:00
Rafael Espindola
96f432c795 Relax the test a bit more to handle different UIDs and GIDs.
llvm-svn: 186186
2013-07-12 19:13:16 +00:00
Rafael Espindola
67d6fae59a Relax test a bit to handle umask differences.
llvm-svn: 186184
2013-07-12 18:54:28 +00:00
Rafael Espindola
55b2c00b7d Add a test for the 'o' option in llvm-ar.
llvm-svn: 186183
2013-07-12 18:51:25 +00:00
Tom Stellard
977376a943 R600/SI: Add support for f64 kernel arguments
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186182
2013-07-12 18:15:26 +00:00
Tom Stellard
ce0acc677f R600/SI: Implement select and compares for SI
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186181
2013-07-12 18:15:19 +00:00
Tom Stellard
f2a3075fdd R600/SI: Add fsqrt pattern for SI
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186180
2013-07-12 18:15:13 +00:00
Tom Stellard
b7b09a29aa R600/SI: Add double precision fsub pattern for SI
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186179
2013-07-12 18:15:08 +00:00
Tom Stellard
43c1f3d80d R600/SI: SI support for 64bit ConstantFP
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186178
2013-07-12 18:15:02 +00:00
Tom Stellard
8b6f62dcb2 R600/SI: Add initial double precision support for SI
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186177
2013-07-12 18:14:56 +00:00
Benjamin Kramer
95a2f42a75 X86: Shrink certain forms of movsx.
In particular:
movsbw %al, %ax   --> cbtw
movswl %ax, %eax  --> cwtl
movslq %eax, %rax --> cltq

According to Intel's manual those have the same performance characteristics but
come with a smaller encoding.

llvm-svn: 186174
2013-07-12 18:06:44 +00:00
Stephen Lin
f8bbffe976 X86: fold SSE2/AVX2 logical shift by immediate amount into zero vector when possible
Patch by Andrea Di Biagio

llvm-svn: 186165
2013-07-12 15:31:36 +00:00
Stephen Lin
c6bb3a6cda Start using CHECK-LABEL in some tests.
llvm-svn: 186163
2013-07-12 14:54:12 +00:00
Stephen Lin
7148920f58 Add new directive called CHECK-LABEL to FileCheck.
CHECK-LABEL is meant to be used in place on CHECK on lines containing identifiers or other unique labels (they need not actually be labels in the source or output language, though.) This is used to break up the input stream into separate blocks delineated by CHECK-LABEL lines, each of which is checked independently. This greatly improves the accuracy of errors and fix-it hints in many cases, and allows for FileCheck to recover from errors in one block by continuing to subsequent blocks.

Some tests will be converted to use this new directive in forthcoming patches.

llvm-svn: 186162
2013-07-12 14:51:05 +00:00
Rafael Espindola
f735609444 Don't reject an empty archive.
llvm-svn: 186159
2013-07-12 13:32:28 +00:00
Chandler Carruth
4163f3fe85 Revert "indvars: Improve LFTR by eliminating truncation when comparing
against a constant."

This reverts commit r186107. It didn't handle wrapping arithmetic in the
loop correctly and thus caused the following C program to count from
0 to UINT64_MAX instead of from 0 to 255 as intended:

  #include <stdio.h>
  int main() {
    unsigned char first = 0, last = 255;
    do { printf("%d\n", first); } while (first++ != last);
  }

Full test case and instructions to reproduce with just the -indvars pass
sent to the original review thread rather than to r186107's commit.

llvm-svn: 186152
2013-07-12 11:18:55 +00:00
Vladimir Medic
8e12e22a4d Add support for Mips break and syscall insructions. The corresponding test cases are added.
llvm-svn: 186151
2013-07-12 09:25:35 +00:00
Richard Sandiford
bab8ad599d [SystemZ] Add test missing from r186148
Sigh, twice in two days sorry.  One day I'll remember...

llvm-svn: 186150
2013-07-12 09:20:14 +00:00
Richard Sandiford
8fe174c649 [SystemZ] Optimize sign-extends of vector setccs
Normal (sext (setcc ...)) sequences are optimised into
(select_cc ..., -1, 0) by DAGCombiner::visitSIGN_EXTEND.
However, this is deliberately not done for vectors, and after
vector type legalization we have (sext_inreg (setcc ...)) instead.

I wondered about trying to extend DAGCombiner to handle this case too,
but it seemed to be a loss on some other targets I tried, even those for
which SETCC isn't "legal" and SELECT_CC is.

llvm-svn: 186149
2013-07-12 09:17:10 +00:00
Richard Sandiford
b7ea44c800 [SystemZ] Improve spilling of LGDR and LDGR
If the source of these instructions is spilled we should load the destination.
If the destination is spilled we should store the source.

llvm-svn: 186147
2013-07-12 08:37:17 +00:00
Nadav Rotem
ee62470368 SLPVectorizer: Sink and enable CSE for ExtractElements.
llvm-svn: 186145
2013-07-12 06:09:24 +00:00
Charles Davis
2b2075f834 Target/X86: Add explicit Win64 and System V/x86-64 calling conventions.
Summary:
This patch adds explicit calling convention types for the Win64 and
System V/x86-64 ABIs. This allows code to override the default, and use
the Win64 convention on a target that wants to use SysV (and
vice-versa). This is needed to implement the `ms_abi` and `sysv_abi` GNU
attributes.

Reviewers:

CC:

llvm-svn: 186144
2013-07-12 06:02:35 +00:00
NAKAMURA Takumi
8e9b7d6d74 llvm/test/Object/archive-toc.test: Use env(1) to satisfy win32 hosts.
llvm-svn: 186143
2013-07-12 02:34:45 +00:00
Nadav Rotem
1e6246b38c SLPVectorize: Replace the code that checks for vectorization candidates in successor blocks with code that scans PHINodes.
Before we could vectorize PHINodes scanning successors was a good way of finding candidates. Now we can vectorize the phinodes which is simpler.

llvm-svn: 186139
2013-07-12 00:04:18 +00:00
David Dean
64322d7020 Add the ability to use guarded malloc when running llvm lit tests.
llvm-svn: 186134
2013-07-11 23:36:57 +00:00
Adrian Prantl
a8066312f8 In response to dblaikie's comment on r186035, replacing the
(reduced LLVM IR) + (full source in comment)
with the
(full LLVM IR) + (reduced src in comment)

llvm-svn: 186119
2013-07-11 21:16:14 +00:00
Rafael Espindola
afa501d655 Add tests for the before and after modifiers.
llvm-svn: 186118
2013-07-11 21:11:55 +00:00
Rafael Espindola
f9a1792687 Add a test for llvm-ar's m operation.
llvm-svn: 186110
2013-07-11 19:09:04 +00:00
Hal Finkel
f153e34eee PPC: Add some missing V_SET0 patterns
We had patterns to match v4i32 immAllZerosV -> V_SET0, but not patterns for
v8i16 (which occurs in the test case) or v16i8. The same was true for
V_SETALLONES (so I added the associated patterns for those as well).

Another bug found by llvm-stress.

llvm-svn: 186108
2013-07-11 17:43:32 +00:00
Andrew Trick
fe577c9f45 indvars: Improve LFTR by eliminating truncation when comparing against a constant.
Patch by Michele Scandale!

Adds a special handling of the case where, during the loop exit
condition rewriting, the exit value is a constant of bitwidth lower
than the type of the induction variable: instead of introducing a
trunc operation in order to match correctly the operand types, it
allows to convert the constant value to an equivalent constant,
depending on the initial value of the induction variable and the trip
count, in order have an equivalent comparison between the induction
variable and the new constant.

llvm-svn: 186107
2013-07-11 17:08:59 +00:00
Hal Finkel
adac2cbb4a PPCDAGToDAGISel::isRunOfOnes should return false on zero
This fixes a bug (found by csmith) at -O0 where we attempt to create a RLWIMI
with an out-of-range operand. Most uses of the isRunOfOnes function are guarded
by a condition that the value is not zero. This was not true in two places, and
in both places a zero input would result in an out-of-rage MB value (= 32).

To fix this, isRunOfOnes returns false on a zero input (and I've remove one
now-redundant guard).

llvm-svn: 186101
2013-07-11 16:31:51 +00:00
Rafael Espindola
f1b5484cf9 Fix a FIXME about the format and add a test.
While at it, use strftime on Unix too and use the thread safe versions
of localtime.

llvm-svn: 186090
2013-07-11 15:35:23 +00:00
Arnold Schwaighofer
a8667081e1 LoopVectorize: Vectorize all accesses in address space zero with unit stride
We can vectorize them because in the case where we wrap in the address space the
unvectorized code would have had to access a pointer value of zero which is
undefined behavior in address space zero according to the LLVM IR semantics.
(Thank you Duncan, for pointing this out to me).

Fixes PR16592.

llvm-svn: 186088
2013-07-11 15:21:55 +00:00
Rafael Espindola
f9f9d1648c Merge these tests.
llvm-svn: 186084
2013-07-11 13:44:10 +00:00
Rafael Espindola
948310c9c0 Use a more unique name to avoid conflicting with directory.ll tests when running
in parallel.

llvm-svn: 186083
2013-07-11 13:31:38 +00:00
Rafael Espindola
d7f85dd49b Add a test for llvm-ar's 'd' operation.
llvm-svn: 186082
2013-07-11 13:24:27 +00:00
Rafael Espindola
3395d4e371 Add tests for the 'x' operation.
llvm-svn: 186081
2013-07-11 13:13:09 +00:00
Richard Sandiford
f53d62a725 [SystemZ] Add testcase missing from r186073
llvm-svn: 186074
2013-07-11 09:10:38 +00:00
Richard Sandiford
e5c5a78828 [SystemZ] Use zeroing form of RISBG for shift-and-AND sequences
Extend r186072 to handle shifts and ANDs.

llvm-svn: 186073
2013-07-11 09:10:09 +00:00
Richard Sandiford
fa42560424 [SystemZ] Use zeroing form of RISBG for some AND sequences
RISBG can handle some ANDs for which no AND IMMEDIATE exists.
It also acts as a three-operand AND for some cases where an
AND IMMEDIATE could be used instead.

It might be worth adding a pass to replace RISBG with AND IMMEDIATE
in cases where the register operands end up being the same and where
AND IMMEDIATE is smaller.

llvm-svn: 186072
2013-07-11 08:59:12 +00:00
Richard Sandiford
c27e0de402 [SystemZ] Allow 8-bit operands to RISBG
RISBG has three 8-bit operands (I3, I4 and I5).  I'd originally
restricted all three to 6 bits, since that's the only range we intended
to use at the time.  However, the top bit of I4 acts as a "zero" flag for
RISBG, while the top bit of I3 acts as a "test" flag for RNSBG & co.
This patch therefore allows them to have the full 8-bit range.
I've left the fifth operand as a 6-bit value for now since the
upper 2 bits have no defined meaning.

llvm-svn: 186070
2013-07-11 08:37:13 +00:00
Duncan Sands
447d97b223 TryToSimplifyUncondBranchFromEmptyBlock was checking that any common
predecessors of the two blocks it is attempting to merge supply the
same incoming values to any phi in the successor block.  This change
allows merging in the case where there is one or more incoming values
that are undef.  The undef values are rewritten to match the non-undef
value that flows from the other edge.  Patch by Mark Lacey.

llvm-svn: 186069
2013-07-11 08:28:20 +00:00