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208 Commits

Author SHA1 Message Date
Evan Cheng
b7bb090d5d Rather than having a ton of patterns for double shift instructions, e.g. SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32). 
llvm-svn: 102485
 2010-04-28 01:18:01 +00:00
Chris Lattner
c5499723d5 fix some modelling problems exposed by a patch I'm working on. bsr/bsf/ptest 
nodes all have an EFLAGS result when made by isel lowering.

llvm-svn: 99736
 2010-03-28 05:07:17 +00:00
Chris Lattner
154641e2ff eliminate the last of the parallel's! 
llvm-svn: 99700
 2010-03-27 02:47:14 +00:00
Chris Lattner
e42b80792e remove 64-bit or_is_add parallels. 
llvm-svn: 99360
 2010-03-24 00:16:52 +00:00
Chris Lattner
3634b075ee remove the patterns that I commented out in r98930, Dan verified 
that they are dead.

llvm-svn: 99000
 2010-03-19 21:43:36 +00:00
Daniel Dunbar
f803121396 MC/X86: Rename alternate spellings of {ADD64,CMP64} and mark as "code gen only" so they don't get selected by the asm matcher. 
llvm-svn: 98972
 2010-03-19 18:07:48 +00:00
Chris Lattner
9ae31faad2 comment out a bunch of parallel store patterns that apparently 
can't match or just have no testcases.  Will remove after 
confirmation from dan that they really are dead.

llvm-svn: 98930
 2010-03-19 04:14:21 +00:00
Daniel Dunbar
3ef39d497f X86: Fix encoding for TEST64rr. 
llvm-svn: 98919
 2010-03-19 01:15:03 +00:00
Chris Lattner
938747fc7f Now that tblgen can handle matching implicit defs of instructions 
to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.

Now we can change things like this:

 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
-                  [(X86cmp RFP80:$lhs, RFP80:$rhs),
-                   (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+                  [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;

and fix terrible crimes like this:

-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
           (TEST8rr GR8:$src1, GR8:$src1)>;

This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.

llvm-svn: 98903
 2010-03-19 00:01:11 +00:00
Chris Lattner
0be133bc3d callq is pcrelative 
llvm-svn: 98835
 2010-03-18 17:52:22 +00:00
Chris Lattner
b91b5cdb03 fix the same bug on the x86-64 side of the fence. 
llvm-svn: 98616
 2010-03-16 06:39:08 +00:00
Evan Cheng
6bc9eccbe4 Fix jit encoding bugs. 
llvm-svn: 98510
 2010-03-14 19:28:34 +00:00
Evan Cheng
7d8c39bb1c Do not force indirect tailcall through fixed registers: eax, r11. Add support to allow loads to be folded to tail call instructions. 
llvm-svn: 98465
 2010-03-14 03:48:46 +00:00
Daniel Dunbar
8b64742f0c X86_64: Fix encoding for the rest of the 64i32 instructions too. 
llvm-svn: 98458
 2010-03-13 22:57:53 +00:00
Daniel Dunbar
a6526284f4 X86: Fix ADD64i32 encoding. 
llvm-svn: 98457
 2010-03-13 22:49:39 +00:00
Daniel Dunbar
6d5fa0c9d6 MC/X86_64: Fix matching of leaq. 
llvm-svn: 98444
 2010-03-13 19:31:44 +00:00
Daniel Dunbar
de2f4ae158 MC/X86_64: Fix matching of callq. 
llvm-svn: 98443
 2010-03-13 19:31:38 +00:00
Chris Lattner
6ba2e68770 Correct immediate sizes. 
llvm-svn: 97957
 2010-03-08 18:55:15 +00:00
Chris Lattner
b178d16c23 factor the 'sign extended from 8 bit' patterns better so 
that they are not destination type specific.  This allows
tblgen to factor them and the type check is redundant with
what the isel does anyway.

llvm-svn: 97629
 2010-03-03 01:45:01 +00:00
Dan Gohman
99c6bcbc13 The mayHaveSideEffects flag is no longer used. 
llvm-svn: 97348
 2010-02-27 23:47:46 +00:00
Chris Lattner
d35abb1c89 fix an incorrect (overly conservative) predicate. 
llvm-svn: 97316
 2010-02-27 08:18:55 +00:00
Chris Lattner
03b5f3e853 remove a bunch of dead named arguments in input patterns, 
though some look dubious afaict, these are all ok.

llvm-svn: 96899
 2010-02-23 06:54:29 +00:00
Chris Lattner
4fb7a4c1c2 fix a type mismatch in this pattern, where we were using an i64 imm in a 
place where an i32 imm was required, the old isel just got lucky.

This fixes CodeGen/X86/x86-64-and-mask.ll

llvm-svn: 96894
 2010-02-23 06:09:57 +00:00
Chris Lattner
5b01ab848c remove special cases for vmlaunch, vmresume, vmxoff, and swapgs 
fix swapgs to be spelled right.

llvm-svn: 96058
 2010-02-13 00:41:14 +00:00
Daniel Dunbar
c82069746b X86: Fix definition for RCL/RCR.*m? operations -- they were getting represented 
with "tied memory operands", which is wrong.

llvm-svn: 95950
 2010-02-12 01:22:03 +00:00
Chris Lattner
7acf9be6c4 move target-independent opcodes out of TargetInstrInfo 
into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687
 2010-02-09 19:54:29 +00:00
Chris Lattner
22151cbec5 really kill off the last MRMInitReg inst, remove logic from encoder. 
llvm-svn: 95437
 2010-02-05 21:34:18 +00:00
Chris Lattner
32f09202d6 factor code better in X86MCInstLower::Lower, teach it to 
lower the SETB* instructions.

llvm-svn: 95431
 2010-02-05 21:13:48 +00:00
Evan Cheng
e86a191862 Change TAILJMP's to be varargs and transfer implicit uses over from TCRETURN's. Otherwise the missing uses can make post-regalloc scheduling do bad things. This fixes 403.gcc. 
llvm-svn: 94950
 2010-01-31 07:28:44 +00:00
Daniel Dunbar
5d1a686840 Mark EH_RETURN64 as CodeGenOnly. 
llvm-svn: 94205
 2010-01-22 20:16:37 +00:00
Evan Cheng
bc0b06fb16 Eliminate or_not_add and just use AddedComplexity so isel tries or_is_add patterns first. 
llvm-svn: 93245
 2010-01-12 18:31:19 +00:00
Dan Gohman
51b3e804dc Reapply the MOV64r0 patch, with a fix: MOV64r0 clobbers EFLAGS. 
llvm-svn: 93229
 2010-01-12 04:42:54 +00:00
Evan Cheng
bd938ebc90 Extend r93152 to work on OR r, r. If the source set bits are known not to overlap, then select as an ADD instead. 
llvm-svn: 93191
 2010-01-11 22:03:29 +00:00
Evan Cheng
bc84a42d7b Revert 93158. It's breaking quite a few x86_64 tests. 
llvm-svn: 93185
 2010-01-11 21:13:41 +00:00
Dan Gohman
541c4f4c5d Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it 
has an immediate with at least 32 bits of leading zeros, to avoid needing to
materialize that immediate in a register first.

FileCheckize, tidy, and extend a testcase to cover this case.

This fixes rdar://7527390.

llvm-svn: 93160
 2010-01-11 17:58:34 +00:00
Dan Gohman
5b79391087 Re-instate MOV64r0 and MOV16r0, with adjustments to work with the 
new AsmPrinter. This is perhaps less elegant than describing them
in terms of MOV32r0 and subreg operations, but it allows the
current register to rematerialize them.

llvm-svn: 93158
 2010-01-11 17:37:57 +00:00
Dan Gohman
a83443605d Pattern top-level operators don't need to be restricted to a 
single user. The _su forms are intended for non-top-level nodes.

llvm-svn: 93155
 2010-01-11 17:21:05 +00:00
Evan Cheng
ee806a0db5 Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed. 
llvm-svn: 93152
 2010-01-11 17:03:47 +00:00
Evan Cheng
4f25f87baa Fix what looks to me obvious instruction definition bugs. 
1. CMPXCHG8B and CMPXCHG16B did not specify implicit physical register defs and uses.
2. LCMPXCHG8B is loading 64 bit memory, not 32 bit.

llvm-svn: 92985
 2010-01-08 01:29:19 +00:00
Evan Cheng
275a43dadb Perform this folding as a target specific dag combine: 
(or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)

The isel patterns may not catch all the cases if general dag combine has reduced width of source operands.

llvm-svn: 92513
 2010-01-04 21:22:48 +00:00
Sean Callanan
06b6feb2e1 Instruction fixes, added instructions, and AsmString changes in the 
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier

llvm-svn: 91638
 2009-12-18 00:01:26 +00:00
Evan Cheng
aaf2f58a04 Re-enable 91381 with fixes. 
llvm-svn: 91489
 2009-12-16 00:53:11 +00:00
Evan Cheng
32946d6aae Fix an encoding bug. 
llvm-svn: 91417
 2009-12-15 06:49:02 +00:00
Evan Cheng
cd8f0de016 Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's. 
llvm-svn: 91381
 2009-12-15 00:53:42 +00:00
Dan Gohman
af05157fde Fix a minor inconsistency. 
llvm-svn: 90165
 2009-11-30 23:33:37 +00:00
Evan Cheng
6e4430374e MOV64rm should be marked isReMaterializable. 
llvm-svn: 89019
 2009-11-17 00:55:55 +00:00
Anton Korobeynikov
9737bfedeb Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364. 
PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
llvm-svn: 85766
 2009-11-02 00:11:39 +00:00
Dan Gohman
2767aa065e Initial x86 support for BlockAddresses. 
llvm-svn: 85557
 2009-10-30 01:28:02 +00:00
Dan Gohman
3393a4c997 Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517
 2009-10-29 18:10:34 +00:00
Chris Lattner
cf8c23d554 remove strings from instructions who are never asmprinted. 
All of these "subreg32" modifier instructions are handled
explicitly by the MCInst lowering phase.  If they got to
the asmprinter, they would explode.  They should eventually
be replace with correct use of subregs.

llvm-svn: 84526
 2009-10-19 19:51:42 +00:00