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Commit Graph

168210 Commits

Author SHA1 Message Date
Philip Reames
bc41d290af [AST] Reorder code to reduce a future patch diff [NFC]
llvm-svn: 340383
2018-08-22 03:33:55 +00:00
Philip Reames
d401425eb2 [AST] Move a function definition into the cpp [NFC]
llvm-svn: 340382
2018-08-22 03:32:52 +00:00
Max Kazantsev
c8eea01630 [GuardWidening] Ignore guards with trivial conditions
Guard widening should not spend efforts on dealing with guards with trivial true/false conditions.
Such guards can easily be eliminated by any further cleanup pass like instcombine. However we
should not unconditionally delete them because it may be profitable to widen other conditions
into such guards.

Differential Revision: https://reviews.llvm.org/D50247
Reviewed By: fedor.sergeev

llvm-svn: 340381
2018-08-22 02:40:49 +00:00
Fangrui Song
8c95eeae9d [gold] -thinlto-object-suffix-replace: don't append new suffix if path does not end with old suffix
Summary: This is to be consistent with lld behavior since rLLD340364.

Reviewers: tejohnson

Reviewed By: tejohnson

Subscribers: steven_wu, eraman, mehdi_amini, inglorion, dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D51060

llvm-svn: 340380
2018-08-22 02:11:36 +00:00
Vedant Kumar
5602b833c9 [CodeGenPrepare] Set debug loc when widening a switch condition
Set a debug location on the cast instruction used to widen a switch
condition.

llvm-svn: 340379
2018-08-22 01:23:31 +00:00
Bob Haarman
2be365cbce [Support][CachePruning] prune least recently accessed files first
Summary:
Before this change, pruning order was based on size. This changes it
to be based on time of last use instead, preferring to keep recently
used files and prune older ones.

Reviewers: pcc, rnk, espindola

Reviewed By: rnk

Subscribers: emaste, arichardson, hiraditya, steven_wu, dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D51062

llvm-svn: 340374
2018-08-22 00:52:16 +00:00
Heejin Ahn
5835a4ffcf [WebAssembly] Fix typos in mem.grow/memory.grow opcodes
This should be not 0x3f but 0x40.

llvm-svn: 340373
2018-08-22 00:33:34 +00:00
Heejin Ahn
b3bb3dc028 [WebAssembly] Change comments on SP writing back (NFC)
Summary: We now write back not to memory but to __stack_pointer global.

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D51074

llvm-svn: 340372
2018-08-22 00:20:02 +00:00
Vedant Kumar
c0dd251e86 [CodeGenPrepare] Set debug locations when splitting selects
When splitting a select into a diamond, set debug locations on
newly-created branch instructions and phi nodes.

llvm-svn: 340371
2018-08-22 00:10:37 +00:00
Vedant Kumar
8314ccb02a [CodeGenPrepare] Clean up dbg.value use-before-def as late as possible
CodeGenPrepare has a strategy for moving dbg.values so that a value's
definition always dominates its debug users. This cleanup was happening
too early (before certain CGP transforms were run), resulting in some
dbg.value use-before-def errors.

Perform this cleanup as late as possible to avoid use-before-def.

llvm-svn: 340370
2018-08-21 23:43:08 +00:00
Vedant Kumar
a5b0ee143f [CodeGenPrepare] Pre-commit debug info test for optimizeSelectInst
This test shows that optimizeSelectInst splits a select and sinks a
`fdiv` operation to one side of the diamond. However, the dbg.value for
the operation isn't moved.

llvm-svn: 340369
2018-08-21 23:42:53 +00:00
Vedant Kumar
b5a8c81ac9 [CodeGenPrepare] Scan past debug intrinsics to find select candidates (NFC)
In optimizeSelectInst, when scanning for candidate selects to rewrite
into branches, scan past debug intrinsics. This makes the debug-enabled
and non-debug paths through optimizeSelectInst more congruent.

NFC because every select is eventually visited either way.

llvm-svn: 340368
2018-08-21 23:42:38 +00:00
Vedant Kumar
a280d7546d [CodeGenPrepare] Exit earlier when optimizing selects (NFC)
When optimizing for size, this allows optimizeSelectInst to skip a
linear scan and exit early.

llvm-svn: 340367
2018-08-21 23:42:23 +00:00
Vedant Kumar
079ae6413d Avoid dbg.value use-before-def in a few tests (NFC)
This is preparation for landing a use-before-def verifier for debug
intrinsics (D46100).

As a drive-by, remove `tail` from debug intrinsic calls because it
doesn't mean anything in that context.

llvm-svn: 340366
2018-08-21 23:42:08 +00:00
Alina Sbirlea
11db533bc4 Update MemorySSA in BasicBlockUtils.
Summary:
Extend BasicBlocksUtils to update MemorySSA.

Subscribers: sanjoy, arsenm, nhaehnle, jlebar, Prazek, llvm-commits

Differential Revision: https://reviews.llvm.org/D45300

llvm-svn: 340365
2018-08-21 23:32:03 +00:00
Alina Sbirlea
0fce4cf258 [MemorySSA] Update comment for move APIs to clarify behavior (NFC).
llvm-svn: 340362
2018-08-21 23:13:02 +00:00
Zachary Turner
9be9e38aa6 [MS Demangler] Print template constructor args.
Previously if you had something like this:

template<typename T>
struct Foo {
  template<typename U>
  Foo(U);
};

Foo F(3.7);

this would mangle as ??$?0N@?$Foo@H@@QEAA@N@Z

and this would be demangled as:

undname:      __cdecl Foo<int>::Foo<int><double>(double)
llvm-undname: __cdecl Foo<int>::Foo<int>(double)

Note the lack of the constructor template parameter in our
demangling.

This patch makes it so we print the constructor argument list.

llvm-svn: 340356
2018-08-21 22:52:52 +00:00
Tom Stellard
26fada24bb MachineScheduler: Refactor setPolicy() to limit computing remaining latency
Summary:
Computing the remaining latency can be very expensive especially
on graphs of N nodes where the number of edges approaches N^2.

This reduces the compile time of a pathological case with the
AMDGPU backend from ~7.5 seconds to ~3 seconds.  This test case has
a basic block with 2655 stores, each with somewhere between 500
and 1500 successors and predecessors.

Reviewers: atrick, MatzeB, airlied, mareko

Reviewed By: mareko

Subscribers: tpr, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D50486

llvm-svn: 340346
2018-08-21 21:48:43 +00:00
Philip Reames
497929765c [LICM] Fix a test so it actualy checks what was meant [NFC]
llvm-svn: 340344
2018-08-21 21:27:26 +00:00
Scott Linder
f19b5a445f [AMDGPU] Consider loads from flat addrspace to be potentially divergent
In general we can't assume flat loads are uniform, and cases where we can prove
they are should be handled through infer-address-spaces.

Differential Revision: https://reviews.llvm.org/D50991

llvm-svn: 340343
2018-08-21 21:24:31 +00:00
Zachary Turner
7a7fb4f525 [MS Demangler] Fix a few more edge cases.
I found these by running llvm-undname over a couple hundred
megabytes of object files generated as part of building chromium.
The issues fixed in this patch are:

  1) decltype-auto return types.
  2) Indirect vtables (e.g. const A::`vftable'{for `B'})
  3) Pointers, references, and rvalue-references to member pointers.

I have exactly one remaining symbol out of a few hundred MB of object
files that produces a name we can't demangle, and it's related to
back-referencing.

llvm-svn: 340341
2018-08-21 21:23:49 +00:00
Zachary Turner
b7d1c521b2 Print "invalid mangled name" when we can't demangle something.
llvm-svn: 340340
2018-08-21 21:23:29 +00:00
Heejin Ahn
3a3822c4bc [WebAssembly] Restore __stack_pointer after catch instructions
Summary:
After the stack is unwound due to a thrown exception, the
`__stack_pointer` global can point to an invalid address. This inserts
instructions that restore `__stack_pointer` global.

Reviewers: jgravelle-google, dschuff

Subscribers: mgorny, sbc100, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D50980

llvm-svn: 340339
2018-08-21 21:23:07 +00:00
Anna Thomas
49cd3aed8b NFC: update the test comments in LV test about early exit loops
llvm-svn: 340337
2018-08-21 21:12:02 +00:00
Thomas Lively
5e7745379a [WebAssembly] v128.const
Summary:
This CL implements v128.const for each vector type. New operand types
are added to ensure the vector contents can be serialized without LEB
encoding. Tests are added for instruction selection, encoding,
assembly and disassembly.

Reviewers: aheejin, dschuff, aardappel

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D50873

llvm-svn: 340336
2018-08-21 21:03:18 +00:00
Fangrui Song
3986243db8 [docs][gold] Fix a typo
llvm-svn: 340335
2018-08-21 21:00:54 +00:00
Marcello Maggioni
d7809fbb5d [LICM] Refactor some AliasSetTracker code to get rid of new/deletes. NFC
Differential Revision: https://reviews.llvm.org/D51024

llvm-svn: 340333
2018-08-21 20:30:14 +00:00
Florian Hahn
916c7f6c7c [CodeExtractor] Use 'normal destination' BB as insert point to store invoke results.
Currently CodeExtractor tries to use the next node after an invoke to
place the store for the result of the invoke, if it is an out parameter
of the region. This fails, as the invoke terminates the current BB.
In that case, we can place the store in the 'normal destination' BB, as
the result will only be available in that case.


Reviewers: davidxl, davide, efriedma

Reviewed By: davidxl

Differential Revision: https://reviews.llvm.org/D51037

llvm-svn: 340331
2018-08-21 20:07:46 +00:00
Heejin Ahn
18d2aa833a [WebAssembly] Don't make wasm cleanuppads into funclet entries
Summary:
Catchpads and cleanuppads are not funclet entries; they are only EH
scope entries. We already dont't set `isEHFuncletEntry` for catchpads.
This patch does the same thing for cleanuppads.

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D50654

llvm-svn: 340330
2018-08-21 20:04:42 +00:00
Heejin Ahn
dc4bfc8462 [WebAssembly] Change writeSPToMemory to writeSPToGlobal (NFC)
Summary: SP is now a __stack_pointer global and not a memory address anymore.

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D51046

llvm-svn: 340328
2018-08-21 19:52:19 +00:00
Bjorn Pettersson
fcd5754b21 [RegisterCoalescer] Use substPhysReg in reMaterializeTrivialDef
Summary:
When RegisterCoalescer::reMaterializeTrivialDef is substituting
a register use in a DBG_VALUE instruction, and the old register
is a subreg, and the new register is a physical register,
then we need to use substPhysReg in order to extract the correct
subreg.

Reviewers: wmi, aprantl

Reviewed By: wmi

Subscribers: hiraditya, MatzeB, qcolombet, tpr, llvm-commits

Differential Revision: https://reviews.llvm.org/D50844

llvm-svn: 340326
2018-08-21 19:47:32 +00:00
Heejin Ahn
8e7bbf9abf [WebAssembly] Add isEHScopeReturn instruction property
Summary:
So far, `isReturn` property is used to mean both a return instruction
from a functon and the end of an EH scope, a scope that starts with a EH
scope entry BB and ends with a catchret or a cleanupret instruction.
Because WinEH uses funclets, all EH-scope-ending instructions are also
real return instruction from a function. But for wasm, they only serve
as the end marker of an EH scope but not a return instruction that
exits a function. This mismatch caused incorrect prolog and epilog
generation in wasm EH scopes. This patch fixes this.

This patch is in the same vein with rL333045, which splits
`MachineBasicBlock::isEHFuncletEntry` into `isEHFuncletEntry` and
`isEHScopeEntry`.

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D50653

llvm-svn: 340325
2018-08-21 19:44:11 +00:00
Simon Pilgrim
a3219fe801 Fix Wdocumentation warning. NFCI.
llvm-svn: 340324
2018-08-21 19:29:39 +00:00
Craig Topper
b599c8ed2b [InstCombine] Pull simple checks above a more complicated one. NFCI
I'm assuming its easier to make sure the RHS of an XOR is all ones than it is to check for the many select patterns we have. So lets check that first. Same with the one use check.

llvm-svn: 340321
2018-08-21 19:17:00 +00:00
Florian Hahn
19ec2ce1e7 [GVN] Assign new value number to calls reading memory, if there is no MemDep info.
Currently we assign the same value number to two calls reading the same
memory location if we do not have MemoryDependence info. Without MemDep
Info we cannot guarantee that there is no store between the two calls, so we
have to assign a new number to the second call.

It also adds a new option EnableMemDep to enable/disable running
MemoryDependenceAnalysis and also renamed NoLoads to NoMemDepAnalysis to
be more explicit what it does. As it also impacts calls that read memory,
NoLoads is a bit confusing.

Reviewers: efriedma, sebpop, john.brawn, wmi

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D50893

llvm-svn: 340319
2018-08-21 19:11:27 +00:00
Krzysztof Parzyszek
07371d478e [RegisterCoalscer] Manually remove leftover segments when commuting def
In removeCopyByCommutingDef, segments from the source live range are
copied into (and merged with) the segments of the target live range.
This is performed for all subranges of the source interval. It can
happen that there will be subranges of the target interval that had
no corresponding subranges in the source interval, and in such cases
these subrages will not be updated. Since the copy being coalesced
is about to be removed, these ranges need to be updated by removing
the segments that are started by the copy.

llvm-svn: 340318
2018-08-21 19:01:26 +00:00
Benjamin Kramer
777f040c71 [NVPTX] Remove ftz variants of cvt with rounding mode
These do not exist in ptxas, it refuses to compile them.

Differential Revision: https://reviews.llvm.org/D51042

llvm-svn: 340317
2018-08-21 18:44:25 +00:00
Matt Davis
787d98fd2a [llvm-mca] Remove unused decl. NFC.
llvm-svn: 340316
2018-08-21 18:39:20 +00:00
Eric Christopher
d0fe42f8dd Temporarily Revert "[PowerPC] Generate Power9 extswsli extend sign and shift immediate instruction" due to it causing a compiler crash on valid.
This reverts commit r340016, testcase forthcoming.

llvm-svn: 340315
2018-08-21 18:35:08 +00:00
Andrea Di Biagio
3225498e2b [llvm-mca] Add the ability to customize the instruction selection strategy in the Scheduler.
The constructor of Scheduler now accepts a SchedulerStrategy object, which is
used internally by method Scheduler::select() to drive the instruction selection
process.

The goal of this patch is to enable the definition of custom selection
strategies while reusing the same algorithms implemented by class Scheduler.
The motivation is that, on some targets, the default strategy may not well
approximate the selection logic in the hardware schedulers.

This patch also adds the ability to pass a ResourceManager object to the
constructor of Scheduler. This gives a bit more flexibility to the design, and
potentially it allows to expose processor resources to SchedulerStrategy
objects.

Differential Revision: https://reviews.llvm.org/D51051

llvm-svn: 340314
2018-08-21 18:20:16 +00:00
Simon Pilgrim
f15d40afe3 [X86][SSE] Add non-uniform udiv test that is mostly divide by 1.
The test demonstrates over-complicated codegen for a udiv that only has one divisor that doesn't equal 1. This should have allowed the codegen to be a lot simpler (uniform shifts etc.) but only the SSE2 manages to make use of this......

llvm-svn: 340313
2018-08-21 18:02:28 +00:00
Philip Reames
8217861627 [AST] Remove notion of volatile from alias sets [NFCI]
Volatility is not an aliasing property. We used to model volatile as if it had extremely conservative aliasing implications, but that hasn't been true for several years now. So, it doesn't make sense to be in AliasSet.

It also turns out the code is entirely a noop. Outside of the AST code to update it, there was only one user: load store promotion in LICM. L/S promotion doesn't need the check since it walks all the users of the address anyway. It already checks each load or store via !isUnordered which causes us to bail for volatile accesses. (Look at the lines immediately following the two remove asserts.)

There is the possibility of some small compile time impact here, but the only case which will get noticeably slower is a loop with a large number of loads and stores to the same address where only the last one we inspect is volatile. This is sufficiently rare it's not worth optimizing for..

llvm-svn: 340312
2018-08-21 17:59:11 +00:00
Yury Delendik
bf75cf8d32 Update DBG_VALUE register operand during LiveInterval operations
Summary:
Handling of DBG_VALUE in ConnectedVNInfoEqClasses::Distribute() was fixed in
PR16110. However DBG_VALUE register operands are not getting updated. This
patch properly resolves the value location.

Reviewers: MatzeB, vsk

Reviewed By: MatzeB

Subscribers: kparzysz, thegameg, vsk, MatzeB, dschuff, sbc100, jgravelle-google, aheejin, sunfish, llvm-commits

Tags: #debug-info

Differential Revision: https://reviews.llvm.org/D48994

llvm-svn: 340310
2018-08-21 17:48:28 +00:00
Aditya Nandakumar
1dea0652da Revert "Revert rr340111 "[GISel]: Add Legalization/lowering code for bit counting operations""
This reverts commit d1341152d91398e9a882ba2ee924147ea2f9b589.

This patch originally made use of Nested MachineIRBuilder buildInstr
calls, and since order of argument processing is not well defined, the
instructions were built slightly in a different order (still correct).
I've removed the nested buildInstr calls to have a defined order now.

Patch was tested by Mikael.

llvm-svn: 340309
2018-08-21 17:30:31 +00:00
Simon Pilgrim
f61226a39c [X86][SSE] Lower vXi8 general shifts to SSE shifts directly. NFCI.
Most of these shifts are extended to vXi16 so we don't gain anything from forcing another round of generic shift lowering - we know these extended cases are legal constant splat shifts.

llvm-svn: 340307
2018-08-21 17:27:03 +00:00
Peter Collingbourne
783d2a816a llvm-readobj: Simplify. NFCI.
llvm-svn: 340305
2018-08-21 17:18:18 +00:00
Craig Topper
7d41e7f535 [BypassSlowDivision] Teach bypass slow division not to interfere with div by constant where constants have been constant hoisted, but not moved from their basic block
DAGCombiner doesn't pay attention to whether constants are opaque before doing the div by constant optimization. So BypassSlowDivision shouldn't introduce control flow that would make DAGCombiner unable to see an opaque constant. This can occur when a div and rem of the same constant are used in the same basic block. it will be hoisted, but not leave the block.

Longer term we probably need to look into the X86 immediate cost model used by constant hoisting and maybe not mark div/rem immediates for hoisting at all.

This fixes the case from PR38649.

Differential Revision: https://reviews.llvm.org/D51000

llvm-svn: 340303
2018-08-21 17:15:33 +00:00
Simon Pilgrim
07b46f9d99 [X86][SSE] Lower v8i16 general shifts to SSE shifts directly. NFCI.
We don't gain anything from forcing another round of generic shift lowering - we know these are legal constant splat shifts.

llvm-svn: 340302
2018-08-21 17:05:07 +00:00
Simon Pilgrim
eb16ddccbf [X86][SSE] Lower directly to SSE shifts in the BLEND(SHIFT, SHIFT) combine. NFCI.
We don't gain anything from forcing another round of generic shift lowering - we know these are legal constant splat shifts.

llvm-svn: 340300
2018-08-21 16:46:48 +00:00
Matt Arsenault
a31d58c739 Try to fix bot build failure
llvm-svn: 340296
2018-08-21 16:24:56 +00:00