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2 Commits

Author SHA1 Message Date
Matt Arsenault
2724c8cef5 AMDGPU: Don't rely on m0 being -1 for GWS offsets 
This only works if the high bits of m0 are also 0, so m0 would have to
be set to 0xffff.

llvm-svn: 366608
 2019-07-19 20:01:24 +00:00
Matt Arsenault
2b192f15b1 AMDGPU: Add intrinsics for DS GWS semaphore instructions 
llvm-svn: 363983
 2019-06-20 21:11:42 +00:00