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12801 Commits

Author SHA1 Message Date
Eric Christopher
bceac3c150 Add a fixme here.
llvm-svn: 146783
2011-12-16 23:42:38 +00:00
Eric Christopher
945c822d26 Extraneous whitespace and 80-col.
llvm-svn: 146780
2011-12-16 23:42:31 +00:00
Nick Lewycky
88e64bacfa Move parts of lib/Target that use CodeGen into lib/CodeGen.
llvm-svn: 146702
2011-12-15 22:58:58 +00:00
Devang Patel
b8b77459d6 Update DebugLoc while merging nodes at -O0.
Patch by Kyriakos Georgiou!

llvm-svn: 146670
2011-12-15 18:21:18 +00:00
Eli Friedman
71c0914b64 Don't try to form FGETSIGN after legalization; it is possible in some cases, but the existing code can't do it correctly. PR11570.
llvm-svn: 146630
2011-12-15 02:07:20 +00:00
Owen Anderson
4f7037cb7c Enable synthesis of FLOG2 and FEXP2 SelectionDAG nodes from libm calls. These are already marked as illegal by default.
llvm-svn: 146623
2011-12-15 00:54:12 +00:00
Dan Gohman
1add31cc93 Move Instruction::isSafeToSpeculativelyExecute out of VMCore and
into Analysis as a standalone function, since there's no need for
it to be in VMCore. Also, update it to use isKnownNonZero and
other goodies available in Analysis, making it more precise,
enabling more aggressive optimization.

llvm-svn: 146610
2011-12-14 23:49:11 +00:00
Devang Patel
0db1ed1a48 Do not sink instruction, if it is not profitable.
On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator.

Radar 10266272.

llvm-svn: 146604
2011-12-14 23:20:38 +00:00
Bill Wendling
7fca2377aa Reapply r146481 with a fix to create the Builder value in the correct place and
with the correct iterator.
<rdar://problem/10530851>

llvm-svn: 146600
2011-12-14 22:45:33 +00:00
Evan Cheng
8d5b09811a Model ARM predicated write as read-mod-write. e.g.
r0 = mov #0
r0 = moveq #1

Then the second instruction has an implicit data dependency on the first
instruction. Sadly I have yet to come up with a small test case that
demonstrate the post-ra scheduler taking advantage of this.

llvm-svn: 146583
2011-12-14 20:00:08 +00:00
NAKAMURA Takumi
f9188630a4 llvm/lib/CodeGen: Fix cmake build since r146542.
llvm-svn: 146550
2011-12-14 03:50:53 +00:00
Eli Friedman
eb387f51bc Add missing cases to SDNode::getOperationName(). Patch by Micah Villmow.
llvm-svn: 146548
2011-12-14 02:28:54 +00:00
Evan Cheng
3257bff430 Allow target to specify register output dependency. Still default to one.
llvm-svn: 146547
2011-12-14 02:28:53 +00:00
Bill Wendling
66a97b48f3 Revert r146481 to review possible miscompilations.
llvm-svn: 146546
2011-12-14 02:18:26 +00:00
Evan Cheng
68ba5536f3 - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
  and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
  prevent IT blocks from being broken apart.

llvm-svn: 146542
2011-12-14 02:11:42 +00:00
Nick Lewycky
b5bf0582aa DW_AT_virtuality is also defined to be constant, not flag.
llvm-svn: 146534
2011-12-14 00:56:07 +00:00
Chad Rosier
281f9442f3 [fast-isel] Remove SelectInsertValue() as fast-isel wasn't designed to handle
instructions that define aggregate types.

llvm-svn: 146492
2011-12-13 17:45:06 +00:00
Bill Wendling
bb813111b6 Avoid using the 'insertvalue' instruction here.
Fast ISel isn't able to handle 'insertvalue' and it causes a large slowdown
during -O0 compilation. We don't necessarily need to generate an aggregate of
the values here if they're just going to be extracted directly afterwards.
<rdar://problem/10530851>

llvm-svn: 146481
2011-12-13 09:22:43 +00:00
Nick Lewycky
ce20cf5c5c DW_AT_accessibility is "constant" class, not form class, so it may not use
DW_FORM_flag. Use DW_FORM_data1 for one byte.

llvm-svn: 146475
2011-12-13 05:09:11 +00:00
Chandler Carruth
e0484f6b37 Initial CodeGen support for CTTZ/CTLZ where a zero input produces an
undefined result. This adds new ISD nodes for the new semantics,
selecting them when the LLVM intrinsic indicates that the undef behavior
is desired. The new nodes expand trivially to the old nodes, so targets
don't actually need to do anything to support these new nodes besides
indicating that they should be expanded. I've done this for all the
operand types that I could figure out for all the targets. Owners of
various targets, please review and let me know if any of these are
incorrect.

Note that the expand behavior is *conservatively correct*, and exactly
matches LLVM's current behavior with these operations. Ideally this
patch will not change behavior in any way. For example the regtest suite
finds the exact same instruction sequences coming out of the code
generator. That's why there are no new tests here -- all of this is
being exercised by the existing test suite.

Thanks to Duncan Sands for reviewing the various bits of this patch and
helping me get the wrinkles ironed out with expanding for each target.
Also thanks to Chris for clarifying through all the discussions that
this is indeed the approach he was looking for. That said, there are
likely still rough spots. Further review much appreciated.

llvm-svn: 146466
2011-12-13 01:56:10 +00:00
Chad Rosier
37852d85ad [fast-isel] Guard "exhastive" fast-isel output with -fast-isel-verbose2.
llvm-svn: 146453
2011-12-13 00:05:11 +00:00
Daniel Dunbar
b72534060e LLVMBuild: Introduce a common section which currently has a list of the
subdirectories to traverse into.
 - Originally I wanted to avoid this and just autoscan, but this has one key
   flaw in that new subdirectories can not automatically trigger a rerun of the
   llvm-build tool. This is particularly a pain when switching back and forth
   between trees where one has added a subdirectory, as the dependencies will
   tend to be wrong. This will also eliminates FIXME implicitly.

llvm-svn: 146436
2011-12-12 22:45:54 +00:00
Pete Cooper
2675c6f8b3 Fixed register allocator splitting a live range on a spilling variable.
If we create new intervals for a variable that is being spilled, then those new intervals are not guaranteed to also spill.  This means that anything reading from the original spilling value might not get the correct value if spills were missed.

Fixes <rdar://problem/10546864>

llvm-svn: 146428
2011-12-12 22:16:27 +00:00
Daniel Dunbar
30d6a45140 LLVMBuild: Remove trailing newline, which irked me.
llvm-svn: 146409
2011-12-12 19:48:00 +00:00
Chad Rosier
2cf6a76fd4 [fast-isel] SelectInsertValue seems to be causing miscompiles for ARM. Disable while I investigate.
llvm-svn: 146331
2011-12-10 21:27:40 +00:00
Chad Rosier
fa991ed762 Typo.
llvm-svn: 146327
2011-12-10 19:48:51 +00:00
Chad Rosier
7e0dc23863 [fast-isel] Add support for selecting insertvalue.
rdar://10530851

llvm-svn: 146276
2011-12-09 20:09:54 +00:00
Evan Cheng
5a218b203a Move isUnpredicatedTerminator() default implementation to TargetInstrInfoImpl to break Target's dependency on CodeGen.
llvm-svn: 146247
2011-12-09 06:41:08 +00:00
Devang Patel
361be2683a Fix comment.
llvm-svn: 146226
2011-12-09 01:25:04 +00:00
Devang Patel
cba55d6c8d Update stale comment.
llvm-svn: 146220
2011-12-09 01:18:48 +00:00
Eli Friedman
8f3db3867c Fix a couple of logic bugs in TargetLowering::SimplifyDemandedBits. PR11514.
llvm-svn: 146219
2011-12-09 01:16:26 +00:00
Devang Patel
a56a1ac691 Revert r146184. I am seeing performance regression cause by this patch in one test case.
llvm-svn: 146205
2011-12-08 23:52:00 +00:00
Owen Anderson
285891eccf Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter can use the former to prevent the formation of libm SDNode's when -fno-builtin is passed.
llvm-svn: 146193
2011-12-08 22:15:21 +00:00
Devang Patel
9680ebaff4 Refactor. No intentional functionality change.
llvm-svn: 146187
2011-12-08 21:48:01 +00:00
Chad Rosier
d0a0415340 Add rather verbose stats for fast-isel failures.
llvm-svn: 146186
2011-12-08 21:37:10 +00:00
Devang Patel
edfacfabb8 Filter "sink to" candidate blocks sooner. This avoids unnecessary computation to determine whether the block dominates all uses or not.
llvm-svn: 146184
2011-12-08 21:33:23 +00:00
Owen Anderson
d003a613e7 Teach SelectionDAG to match more calls to libm functions onto existing SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise.
llvm-svn: 146171
2011-12-08 19:32:14 +00:00
Evan Cheng
320b2be38c Make MachineInstr instruction property queries more flexible. This change all
clients to decide whether to look inside bundled instructions and whether
the query should return true if any / all bundled instructions have the
queried property.

llvm-svn: 146168
2011-12-08 19:23:10 +00:00
Nadav Rotem
341b30a457 Fix a bug in the integer-promotion of bitcast operations on vector types.
We must not issue a bitcast operation for integer-promotion of vector types, because the
location of the values in the vector may be different.

llvm-svn: 146150
2011-12-08 13:10:01 +00:00
Pete Cooper
5e48c1e8e3 Reverting r145899 as it breaks clang self-hosting
llvm-svn: 146136
2011-12-08 03:24:10 +00:00
Eli Friedman
e68dd964f7 Make sure we correctly set LiveRegGens when a call is unscheduled. <rdar://problem/10460321>. No testcase because this is very sensitive to scheduling.
llvm-svn: 146087
2011-12-07 22:24:28 +00:00
Eli Friedman
333928a702 Fix an assertion in the scheduler. PR11386. No testcase included because it's rather delicate.
llvm-svn: 146083
2011-12-07 22:06:02 +00:00
Nick Lewycky
9139ac9fdb These global variables aren't thread-safe, STATISTIC is. Andy Trick tells me
that he isn't using these any more, so just delete them.

llvm-svn: 146076
2011-12-07 21:35:59 +00:00
Jakub Staszak
a8a18f2cf5 Remove unneeded semicolon.
Skip two looking up at BlockChain.

llvm-svn: 146053
2011-12-07 19:46:10 +00:00
Evan Cheng
1acd685d87 Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026
2011-12-07 07:15:52 +00:00
Eli Friedman
e74e55c372 Zap unnecessary isIntDivCheap() check. PR11485. No testcase because this doesn't affect any in-tree target.
llvm-svn: 146015
2011-12-07 03:55:52 +00:00
Jakob Stoklund Olesen
c1f4115eb1 Add missing check.
llvm-svn: 146004
2011-12-07 01:08:22 +00:00
Eli Friedman
9e8d557cd1 Support vector bitcasts in the AsmPrinter. PR11495.
llvm-svn: 146001
2011-12-07 00:50:54 +00:00
Jakob Stoklund Olesen
e612fdbbab Add MachineOperand IsInternalRead flag.
This flag is used when bundling machine instructions.  It indicates
whether the operand reads a value defined inside or outside its bundle.

llvm-svn: 145997
2011-12-07 00:22:07 +00:00
Eli Friedman
5545db0906 Fix an optimization involving EXTRACT_SUBVECTOR in DAGCombine so it behaves correctly. PR11494.
llvm-svn: 145996
2011-12-07 00:11:56 +00:00