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3 Commits

Author SHA1 Message Date
Rafael Espindola
ae2d1c53c7 change the addressing mode of the str instruction to reg+imm 
llvm-svn: 29571
 2006-08-08 20:35:03 +00:00
Rafael Espindola
071c83dff0 create the raddr addressing mode that matches any register and the frame index 
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot

llvm-svn: 29079
 2006-07-10 01:41:35 +00:00
Rafael Espindola
dd49dfc0df added a skeleton of the ARM backend 
llvm-svn: 28301
 2006-05-14 22:18:28 +00:00