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Commit Graph

197638 Commits

Author SHA1 Message Date
Ehud Katz
7c9434aa64 [tests] Fix AMDGPU test
Fix naming issue in test due to change D80399.
2020-05-29 22:15:26 +03:00
Stanislav Mekhanoshin
4a90cb8fa1 [AMDGPU] Regenrated urem/udiv global isel tests. NFC. 2020-05-29 12:08:47 -07:00
Sourabh Singh Tomar
d31dfbc89d [DWARF5] Replace emission of strp with stx forms in debug_macro section
DW_MACRO_define_strx forms are supported now in llvm-dwarfdump and these
forms can be used in both debug_macro[.dwo] sections. An added advantage
for using strx forms over strp forms is that it uses indices
approach instead of a relocation to debug_str section.

This patch unify the emission for debug_macro section.

Reviewed by: dblaikie, ikudrin

Differential Revision: https://reviews.llvm.org/D78865
2020-05-30 00:24:09 +05:30
Sourabh Singh Tomar
f759367eb0 [DWARF5] Added support for .debug_macro.dwo section in llvm-dwarfdump
This patch extends the parsing and dumping support of llvm-dwarfdump
for debug_macro.dwo section.

Following forms are supported:

 - DW_MACRO_define
 - DW_MACRO_undef
 - DW_MACRO_start_file
 - DW_MACRO_end_file
 - DW_MACRO_define_strx
 - DW_MACRO_undef_strx
 - DW_MACRO_define_strp
 - DW_MACRO_undef_strp

Reviewed by: ikudrin, dblaikie

Differential Revision: https://reviews.llvm.org/D78500
2020-05-30 00:12:50 +05:30
Christopher Tetreault
eb757fcbf8 [SVE] Eliminate calls to default-false VectorType::get() from Vectorize
Reviewers: efriedma, c-rhodes, david-arm, fhahn

Reviewed By: david-arm

Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80339
2020-05-29 11:31:24 -07:00
Ehud Katz
ebe25b403e [Local] Prevent invertCondition from creating a redundant instruction
Prevent `invertCondition` from creating the inversion instruction, in
case the given value is an argument which has already been inverted.
Note that this approach has already been taken in case the given value
is an instruction (and not an argument).

Differential Revision: https://reviews.llvm.org/D80399
2020-05-29 21:08:22 +03:00
Sam Clegg
4052b885d0 [WebAssembly] Add placeholders for R_WASM_TABLE_INDEX_REL_SLEB relocations
Previously in the object format we punted on this and simply wrote
zeros (and didn't include the function in the elem segment).  With
this change we write a meaningful value which is the segment
relative table index of the associated function.

This matches the that wasm-ld produces in `-r` mode.  This inconsistency
between the output the MC object writer and the wasm-ld object
writer could cause warnings to be emitted when reading back in the
output of `wasm-ld -r`.  See:
https://github.com/emscripten-core/emscripten/issues/11217

This only applies to this one relocation type which is only generated
when compiling in PIC mode.

Differential Revision: https://reviews.llvm.org/D80774
2020-05-29 10:57:26 -07:00
Sanjay Patel
49bcc8a887 [SLP] auto-generate complete test checks; NFC 2020-05-29 13:45:25 -04:00
Craig Topper
bf3d8d376b [X86] Ignore large code model in X86FastISel::X86MaterializeFP in 32-bit mode
Large code model doesn't mean anything to 32-bit mode. But nothing
prevents it from being set. Ignore to avoid generating 64-bit mode
only instructions.

Differential Revision: https://reviews.llvm.org/D80768
2020-05-29 10:39:08 -07:00
Anna Bulanova
68c4bb3cce [SVE] Replace deprecated call in changeVectorElementTypeToInteger
Summary:
Replace getVectorNumElements with getVectorElementCount;
gets rid of the warnings in several tests

Reviewers: sdesmalen, kmclaughlin, dancgr, efriedma, each, andwar, rengolin

Reviewed By: efriedma

Subscribers: tschuett, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80746
2020-05-29 13:27:28 -04:00
Craig Topper
ed97f5f97b [X86] Remove isel pattern for MMX_X86movdq2q+simple_load. Replace with DAG combine to to loadmmx.
Only 64-bit bits will be loaded, not the whole 128 bits. We can
just combine it to plain mmx load. This has the side effect of
enabling isel load folding for it.

This part of my desire to get rid of isel patterns that shrink loads.
2020-05-29 10:20:03 -07:00
Ehud Katz
c0f1b37259 [PrintSCC] Fix printing a basic-block without a name
Print a basic-block as an operand to handle the case where it has no
name.

Differential Revision: https://reviews.llvm.org/D80552
2020-05-29 20:14:19 +03:00
Sanjay Patel
3e899294e4 [LoopVectorize] auto-generate complete test checks; NFC 2020-05-29 13:14:08 -04:00
Xiangling Liao
0bd0801218 [AIX] Emit AvailableExternally Linkage on AIX
Since on AIX, our strategy is to not use -u to suppress any undefined
symbols, we need to emit .extern for the symbols with AvailableExternally
linkage.

Differential Revision: https://reviews.llvm.org/D80642
2020-05-29 13:12:59 -04:00
Sanjay Patel
f24277f06b [LoopVectorize] regenerate test checks; NFC
Align attributes are now visible.
2020-05-29 13:02:45 -04:00
Sanjay Patel
23492f63e6 [LoopVectorize] auto-generate complete checks; NFC 2020-05-29 13:01:35 -04:00
Sanjay Patel
9a664bc0fd [LoopVectorize] regenerate test checks; NFC
Align attributes are now visible.
2020-05-29 13:01:35 -04:00
Sanjay Patel
587c9ecb53 [LoopVectorize] auto-generate complete test checks; NFC 2020-05-29 13:01:35 -04:00
Paul Robinson
779240e097 Preserve DbgLoc when DeadArgumentElimination rewrites a 'ret'.
Fixes PR46002.
2020-05-29 10:00:33 -07:00
David Green
fb0b1c4e48 [ConstantFolding] Constant folding for integer vector reduce intrinsics
This add constant folding for all the integer vector reduce intrinsics,
providing that the argument is a constant vector. zeroinitializer always
produces 0 for all intrinsics, and other values can be handled with
APInt operators.

Differential Revision: https://reviews.llvm.org/D80516
2020-05-29 17:58:42 +01:00
Guozhi Wei
7118b8a8dd [DAGCombiner] Add command line options to guard store width reduction
optimizations

As discussed in the thread http://lists.llvm.org/pipermail/llvm-dev/2020-May/141838.html,
some bit field access width can be reduced by ReduceLoadOpStoreWidth, some
can't. If two accesses are very close, and the first access width is reduced,
the second is not. Then the wide load of second access will be stalled for long
time.

This patch add command line options to guard ReduceLoadOpStoreWidth and
ShrinkLoadReplaceStoreWithStore, so users can use them to disable these
store width reduction optimizations.

Differential Revision: https://reviews.llvm.org/D80745
2020-05-29 09:41:41 -07:00
Kevin P. Neal
a82170f56f [X86] Fix errors in use of strictfp attribute.
Errors spotted with use of: https://reviews.llvm.org/D68233
2020-05-29 12:31:55 -04:00
Stanislav Mekhanoshin
1dd87bd3d5 GlobalISel: fix CombinerHelper::matchEqualDefs()
This matcher was always returning true for the different
results of a same instruction.

Differential Revision:
2020-05-29 09:30:02 -07:00
Kevin P. Neal
1be46a139e Fix errors in use of strictfp attribute.
Errors spotted with use of: https://reviews.llvm.org/D68233
2020-05-29 12:28:14 -04:00
Kevin P. Neal
132921747f Fix errors in use of strictfp attribute.
Errors spotted with use of: https://reviews.llvm.org/D68233
2020-05-29 12:25:13 -04:00
Kevin P. Neal
cba13ecb55 Fix errors in use of strictfp attribute.
Errors spotted with use of: https://reviews.llvm.org/D68233
2020-05-29 12:22:21 -04:00
David Sherwood
bff701c7ed [CodeGen] Fix warning in visitShuffleVector
Make sure we only ask for the number of elements after we've
bailed out for scalable vectors.

Differential revision: https://reviews.llvm.org/D80632
2020-05-29 17:09:59 +01:00
Jay Foad
6111baefa5 [AMDGPU] Remove duplicate test cases
The two "2sin" test cases were identical to the "sin_2x" test cases just
above.
2020-05-29 16:36:36 +01:00
David Green
9a7508e506 [ARM] Extra MVE VMLAV reduction patterns
These patterns for i8 and i16 VMLA's were missing. They end up from
legalized vector.reduce.add.v8i16 and vector.reduce.add.v16i8, and
although the instruction works differently (the mul and add are
performed in a higher precision), I believe it is OK because only an
i8/i16 are demanded from them, and so the results will be the same. At
least, they pass any testing I can think to run on them.

There are some tests that end up looking worse, but are quite artificial
due to passing half vector types through a call boundary. I would not
expect the vmull to realistically come up like that, and a vmlava is
likely better a lot of the time.

Differential Revision: https://reviews.llvm.org/D80524
2020-05-29 16:23:24 +01:00
diggerlin
9c47d494f8 [AIX][XCOFF] add symbol priority for the llvm-objdump -D -symbol-description
SUMMARY:
when there are two symbol has the same address. llvm-objdump -D -symbol-description will select symbol based on the following rule:

1. using Label first if there is a Label symbol.
2. If there is not Label, using a symbol which has Storage Mapping class.
3. if more than one symbol has storage mapping class, put the TC0 has the low priority, for other storage mapping class , compare based on the value.

Reviewers: James Henderson ,hubert.reinterpretcast,

Differential Revision: https://reviews.llvm.org/D78387
2020-05-29 11:08:51 -04:00
Pushpinder Singh
339fbbae32 Remove SVN logic from find_first_existing_vc_file
As LLVM has moved from SVN to git, there is no need to
keep SVN related code. Also, this code piece was never used.

Differential Revision: https://reviews.llvm.org/D79400
2020-05-29 20:31:55 +05:30
Pushpinder Singh
760d781e95 Fix build failure when source is read only
cmake configure fails when it tries to setup target for llvm_vcsrevision_h
This happens only when source is checked out using repo in a read
only filesystem, because cmake tries to create `.git/logs/HEAD` file.

This patch:
  1. Recovers from failure gracefully.
  2. Ensures that VCSRevision.h is successfully created and updated
     in above scenarios.

Differential Revision: https://reviews.llvm.org/D79400
2020-05-29 20:04:22 +05:30
David Sherwood
9a37a41b33 [SVE] Remove getNumElements() calls in visitGetElementPtrInst
Replace calls to getNumElements() with getElementCount() in order
to avoid warnings for scalable vectors. The warnings were discovered
by this existing test:

  test/CodeGen/AArch64/sve-gep.ll

Differential revision: https://reviews.llvm.org/D80782
2020-05-29 15:26:44 +01:00
David Sherwood
d64d828469 [CodeGen] Fix warnings in LowerToPredicatedOp
When creating a new vector type based on another vector type we
should pass in the element count instead of the number of elements
and scalable flag separately.

I encountered this warning whilst compiling this test:

  CodeGen/AArch64/sve-intrinsics-int-compares.ll

Differential revision: https://reviews.llvm.org/D80621
2020-05-29 15:19:03 +01:00
Hendrik Greving
6f64591fa4 [ModuloSchedule] Allow illegal phis to be moved across stages.
Fixes a trivial but impactful bug where we did not move illegal phis across stages. This
led to incorrect mappings in certain cases.
2020-05-29 07:01:27 -07:00
Georgii Rymar
17fec031fa [llvm-readobj] - Cleanup the DwarfCFIEH::PrinterContext class. NFCI.
It would be nice to switch to `reportUniqueWarnings` from
`reportError` in this class, but first of all it needs a cleanup.

This patch:
1) Eliminates autos.
2) Removes code duplication.
3) Changes how the code works with `Expected<>`.
4) Introduces 2 new `using`s to make the code a bit shorter.

Differential revision: https://reviews.llvm.org/D80726
2020-05-29 16:45:18 +03:00
Sanjay Patel
07aa15d865 [DAGCombiner] avoid unnecessary indirection from SDNode/SDValue; NFCI 2020-05-29 09:31:52 -04:00
Igor Kudrin
c2113b68ec [llvm-objcopy][ELF] Fix removing a group member.
When a group member is removed, the corresponding record in the
SHT_GROUP section has to be deleted.

This fixes PR46064.

Differential Revision: https://reviews.llvm.org/D80568
2020-05-29 20:24:53 +07:00
Igor Kudrin
786d96db56 [llvm-objcopy][ELF] Fix removing SHT_GROUP sections.
When a SHT_GROUP section is removed, but other sections of the group are
kept, the SHF_GROUP flag of these sections should be dropped, otherwise
the resulting ELF file will be malformed.

Differential Revision: https://reviews.llvm.org/D80511
2020-05-29 20:24:53 +07:00
Simon Pilgrim
6837e69bdf TextStubCommon.h - move StringSwitch.h include to TextStubCommon.cpp. NFC.
Only TextStubCommon.cpp actually uses StringSwitch
2020-05-29 14:03:15 +01:00
Simon Pilgrim
ed94dab7d0 TextAPIContext.h - remove unused MemoryBuffer.h include. NFC. 2020-05-29 14:03:15 +01:00
Sanjay Patel
c21b619547 [AArch64][x86] add tests for FMA combines; NFC 2020-05-29 08:58:37 -04:00
Florian Hahn
855b755233 [DAGComb] Do not turn insert_elt into shuffle for single elt vectors.
Currently combineInsertEltToShuffle turns insert_vector_elt into a
vector_shuffle, even if the inserted element is a vector with a single
element. In this case, it should be unlikely that the additional shuffle
would be more efficient than a insert_vector_elt.

Additionally, this fixes a infinite cycle in DAGCombine, where
combineInsertEltToShuffle turns a insert_vector_elt into a shuffle,
which gets turned back into a insert_vector_elt/extract_vector_elt by
a custom AArch64 lowering (in visitVECTOR_SHUFFLE).

Such insert_vector_elt and extract_vector_elt combinations can be
lowered efficiently using mov on AArch64.

There are 2 test changes in arm64-neon-copy.ll: we now use one or two
mov instructions instead of a single zip1. The reason that we need a
second mov in ins1f2 is that we have to move the result to the result
register and is not really related to the DAGCombine fold I think.
But in any case, on most uarchs, mov should be cheaper than zip1. On a
Cortex-A75 for example, zip1 is twice as expensive as mov
(https://developer.arm.com/docs/101398/latest/arm-cortex-a75-software-optimization-guide-v20)

Reviewers: spatel, efriedma, dmgreen, RKSimon

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D80710
2020-05-29 13:21:13 +01:00
Xing GUO
8717026000 [ObjectYAML][DWARF] Make the PubSection optional.
This patch helps make the `PubSection` optional in the DWARF structure.

Reviewed By: jhenderson, aprantl

Differential Revision: https://reviews.llvm.org/D80722
2020-05-29 20:11:53 +08:00
Simon Pilgrim
104d358d14 [CGP] Ensure address scaled offset is representable as int64_t
AddressingModeMatcher::matchScaledValue was calling getSExtValue for a constant before ensuring that we can actually represent the value as int64_t

Fixes OSSFuzz#22723 which is a followup to rGc479052a74b2 (PR46004 / OSSFuzz#22357)
2020-05-29 12:25:43 +01:00
Paul Walker
a604bdd390 [SelectionDAG] Update getNode asserts for EXTRACT/INSERT_SUBVECTOR.
Summary:
The description of EXTACT_SUBVECTOR and INSERT_SUBVECTOR has been
changed to accommodate scalable vectors (see ISDOpcodes.h). This
patch updates the asserts used to verify these requirements when
using SelectionDAG's getNode interface.

This patch introduces the MVT function getVectorMinNumElements
that can be used against fixed-length and scalable vectors when
only the known minimum vector length is required.

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80709
2020-05-29 11:02:18 +00:00
Louis Dionne
47070492b5 [lit] Add an option to print all features used in tests
Lit test suites can tend to accumulate annotations that are not necessarily
relevant as time goes by, for example XFAILS on old compilers or platforms.
To help spot old annotations that can be cleaned up, it can be useful to
look at all features used inside a test suite.

This commit adds a new Lit option '--show-used-features' that prints all
the features used in XFAIL, REQUIRES and UNSUPPORTED of all tests that
are discovered.

Differential Revision: https://reviews.llvm.org/D78589
2020-05-29 07:00:05 -04:00
Florian Hahn
c5b8c59aa2 [SCCP] Switch to widen at PHIs, stores and call edges.
Currently SCCP does not widen PHIs, stores or along call edges
(arguments/return values), but on operations that directly extend ranges
(like binary operators).

This means PHIs, stores and call edges are not pessimized by widening
currently, while binary operators are. The main reason for widening
operators initially was that opting-out for certain operations was
more straight-forward in the initial implementation (and it did not
matter too much, as range support initially was only implemented for a
very limited set of operations.

During the discussion in D78391, it was suggested to consider flipping
widening to PHIs, stores and along call edges. After adding support for
tracking the number of range extensions in ValueLattice, limiting the
number of range extensions per value is straight forward.

This patch introduces a MaxWidenSteps option to the MergeOptions,
limiting the number of range extensions per value. For PHIs, it seems
natural allow an extension for each (active) incoming value plus 1. For
the other cases, a arbitrary limit of 10 has been chosen initially. It would
potentially make sense to set it depending on the users of a
function/global, but that still needs investigating. This potentially
leads to more state-changes and longer compile-times.

The results look quite promising (MultiSource, SPEC):

Same hash: 179 (filtered out)
Remaining: 58
Metric: sccp.IPNumInstRemoved

Program                                        base    widen-phi diff
 test-suite...ks/Prolangs-C/agrep/agrep.test    58.00   82.00    41.4%
 test-suite...marks/SciMark2-C/scimark2.test    32.00   43.00    34.4%
 test-suite...rks/FreeBench/mason/mason.test     6.00    8.00    33.3%
 test-suite...langs-C/football/football.test   104.00  128.00    23.1%
 test-suite...cations/hexxagon/hexxagon.test    36.00   42.00    16.7%
 test-suite...CFP2000/177.mesa/177.mesa.test   214.00  249.00    16.4%
 test-suite...ngs-C/assembler/assembler.test    14.00   16.00    14.3%
 test-suite...arks/VersaBench/dbms/dbms.test    10.00   11.00    10.0%
 test-suite...oxyApps-C++/miniFE/miniFE.test    43.00   47.00     9.3%
 test-suite...ications/JM/ldecod/ldecod.test   179.00  195.00     8.9%
 test-suite...CFP2006/433.milc/433.milc.test   249.00  265.00     6.4%
 test-suite.../CINT2000/175.vpr/175.vpr.test    98.00  104.00     6.1%
 test-suite...peg2/mpeg2dec/mpeg2decode.test    70.00   74.00     5.7%
 test-suite...CFP2000/188.ammp/188.ammp.test    71.00   75.00     5.6%
 test-suite...ce/Benchmarks/PAQ8p/paq8p.test   111.00  117.00     5.4%
 test-suite...ce/Applications/Burg/burg.test    41.00   43.00     4.9%
 test-suite...000/197.parser/197.parser.test    66.00   69.00     4.5%
 test-suite...tions/lambda-0.1.3/lambda.test    23.00   24.00     4.3%
 test-suite...urce/Applications/lua/lua.test   301.00  313.00     4.0%
 test-suite...TimberWolfMC/timberwolfmc.test    76.00   79.00     3.9%
 test-suite...lications/ClamAV/clamscan.test   991.00  1030.00    3.9%
 test-suite...plications/d/make_dparser.test    53.00   55.00     3.8%
 test-suite...fice-ispell/office-ispell.test    83.00   86.00     3.6%
 test-suite...lications/obsequi/Obsequi.test    28.00   29.00     3.6%
 test-suite.../Prolangs-C/bison/mybison.test    56.00   58.00     3.6%
 test-suite.../CINT2000/254.gap/254.gap.test   170.00  176.00     3.5%
 test-suite.../Applications/lemon/lemon.test    30.00   31.00     3.3%
 test-suite.../CINT2000/176.gcc/176.gcc.test   1202.00 1240.00    3.2%
 test-suite...pplications/treecc/treecc.test    79.00   81.00     2.5%
 test-suite...chmarks/MallocBench/gs/gs.test   357.00  366.00     2.5%
 test-suite...eeBench/analyzer/analyzer.test   103.00  105.00     1.9%
 test-suite...T2006/445.gobmk/445.gobmk.test   1697.00 1724.00    1.6%
 test-suite...006/453.povray/453.povray.test   1812.00 1839.00    1.5%
 test-suite.../Benchmarks/Bullet/bullet.test   337.00  342.00     1.5%
 test-suite.../CINT2000/252.eon/252.eon.test   426.00  432.00     1.4%
 test-suite...T2000/300.twolf/300.twolf.test   214.00  217.00     1.4%
 test-suite...pplications/oggenc/oggenc.test   244.00  247.00     1.2%
 test-suite.../CINT2006/403.gcc/403.gcc.test   4008.00 4055.00    1.2%
 test-suite...T2006/456.hmmer/456.hmmer.test   175.00  177.00     1.1%
 test-suite...nal/skidmarks10/skidmarks.test   430.00  434.00     0.9%
 test-suite.../Applications/sgefa/sgefa.test   115.00  116.00     0.9%
 test-suite...006/447.dealII/447.dealII.test   1082.00 1091.00    0.8%
 test-suite...6/482.sphinx3/482.sphinx3.test   141.00  142.00     0.7%
 test-suite...ocBench/espresso/espresso.test   152.00  153.00     0.7%
 test-suite...3.xalancbmk/483.xalancbmk.test   4003.00 4025.00    0.5%
 test-suite...lications/sqlite3/sqlite3.test   548.00  551.00     0.5%
 test-suite...marks/7zip/7zip-benchmark.test   5522.00 5551.00    0.5%
 test-suite...nsumer-lame/consumer-lame.test   208.00  209.00     0.5%
 test-suite...:: External/Povray/povray.test   1556.00 1563.00    0.4%
 test-suite...000/186.crafty/186.crafty.test   298.00  299.00     0.3%
 test-suite.../Applications/SPASS/SPASS.test   2019.00 2025.00    0.3%
 test-suite...ications/JM/lencod/lencod.test   8427.00 8449.00    0.3%
 test-suite...6/464.h264ref/464.h264ref.test   6797.00 6813.00    0.2%
 test-suite...6/471.omnetpp/471.omnetpp.test   431.00  430.00    -0.2%
 test-suite...006/450.soplex/450.soplex.test   446.00  447.00     0.2%
 test-suite...0.perlbench/400.perlbench.test   1729.00 1727.00   -0.1%
 test-suite...000/255.vortex/255.vortex.test   3815.00 3819.00    0.1%

Reviewers: efriedma, nikic, davide

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D79036
2020-05-29 11:59:17 +01:00
Kadir Cetinkaya
6c544d572f [readobj] Fix dangling else warning 2020-05-29 12:55:25 +02:00
David Sherwood
87771f8fd7 [CodeGen] Fix warnings in getZeroExtendInReg
We should be using getVectorElementCount() to assert that two types
have the same numbers of elements. I encountered the warnings while
compiling this test:

  CodeGen/AArch64/sve-intrinsics-ld1.ll

Differential Revision: https://reviews.llvm.org/D80616
2020-05-29 11:51:07 +01:00