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Commit Graph

198145 Commits

Author SHA1 Message Date
Mitch Phillips
bdf48658a5 [HWASan] Add sizeof(global) in report even if symbols missing.
Summary: Refactor the current global header iteration to be callback-based, and add a feature that reports the size of the global variable during reporting. This allows binaries without symbols to still report the size of the global variable, which is always available in the HWASan globals PT_NOTE metadata.

Reviewers: eugenis, pcc

Reviewed By: pcc

Subscribers: mgorny, llvm-commits, #sanitizers

Tags: #sanitizers, #llvm

Differential Revision: https://reviews.llvm.org/D80599
2020-06-09 13:02:13 -07:00
Mitch Phillips
d22f339338 Rebase. 2020-06-09 13:01:40 -07:00
Mitch Phillips
92d9e2416e remove redundant comment about Android. 2020-06-09 13:01:40 -07:00
Mitch Phillips
0d12bc0c5c Address Peter's comments. 2020-06-09 13:01:40 -07:00
Mitch Phillips
8e0a0632f6 Move DSO dependencies inside the group. 2020-06-09 13:01:40 -07:00
Mitch Phillips
66f97bec03 Patch up issues with GN builds (pthread / libz)
Summary:
Fixes up two small issues with the gn build.

 1 - Ensures that the correct ldflag `-pthread` is provided, not just linking the library.
 2 - Ensures that libraries are linked in the same group as the dependencies. This fixes a problem where system libraries (libc) are involved in a link-order dependency that's not being fulfilled.

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80591
2020-06-09 13:01:40 -07:00
LLVM GN Syncbot
ba43bfaf7d [gn build] Port d5c28c40943 2020-06-09 19:53:21 +00:00
Craig Topper
461e54845b [X86] Move CPUKind enum from clang to llvm/lib/Support. NFCI
Similar to what some other targets have done. This information
could be reused by other frontends so doesn't make sense to live
in clang.

-Rename CK_Generic to CK_None to better reflect its illegalness.
-Move function for translating from string to enum into llvm.
-Call checkCPUKind directly from the string to enum translation
and update CPU kind to CK_None accordinly. Caller will use CK_None
as sentinel for bad CPU.

I'm planning to move all the CPU to feature mapping out next. As
part of that I want to devise a better way to express CPUs inheriting
features from an earlier CPU. Allowing this to be expressed in a
less rigid way than just falling through a switch. Or using gotos
as we've had to do lately.

Differential Revision: https://reviews.llvm.org/D81439
2020-06-09 12:52:41 -07:00
Matt Arsenault
349dba66b1 AMDGPU/GlobalISel: Add new baseline tests for bitcast legalization 2020-06-09 15:46:53 -04:00
Sanjay Patel
5fca27122d [x86] refine conditions for immediate hoisting to save code-size
As shown in PR46237:
https://bugs.llvm.org/show_bug.cgi?id=46237

The size-savings win for hoisting an 8-bit ALU immediate (intentionally
excluding store constants) requires extreme conditions; it may not even
be possible when including REX prefix bytes on x86-64.

I did draft a version of this patch that included use counts after the
loop, but I suspect that accounting is not working as expected. I think
that is because the number of constant uses are changing as we select
instructions (for example as we transform shl/add into LEA).

Differential Revision: https://reviews.llvm.org/D81468
2020-06-09 15:44:55 -04:00
Matt Arsenault
0f6cb1fbd8 GlobalISel: Set instr/debugloc before any legalizer action
It was annoying enough that every custom lowering needed to set the
insert point, but this was made worse since now these all needed to be
updated to setInstrAndDebugLoc. Consolidate these so every
legalization action has the right insert position by default.

This should fix dropping debug info in every custom AMDGPU
legalization.
2020-06-09 15:37:02 -04:00
Sanjay Patel
43a7913d37 [InstCombine] add tests for diff-of-sums; NFC 2020-06-09 15:33:38 -04:00
Matt Arsenault
832e0c0296 GlobalISel: Improve MachineIRBuilder construction
The current relationship between LegalizerHelper and MachineIRBuilder
confuses me, because the LegalizerHelper modifies the MachineIRBuilder
which it does not own. Constructing a LegalizerHelper destroys the
insert point, since the constructor calls setMF, which clears all the
fields. Try to separate these functions, so it's possible to construct
a LegalizerHelper from an existing MachineIRBuilder without losing the
insert point/debug loc.
2020-06-09 15:05:04 -04:00
Matt Arsenault
1f25ea44b1 GlobalISel: Move some trivial MIRBuilder methods into the header
The construction APIs for MachineIRBuilder don't make much sense, and
it's been annoying to sort through it with these trivial functions
separate from the declaration.
2020-06-09 15:04:48 -04:00
Matt Arsenault
a27bd6c289 GlobalISel: Remove redundant check in verifier
This was already checked earlier for all instructions.
2020-06-09 15:04:27 -04:00
Matt Arsenault
679926bcca GlobalISel: Fix double printing new instructions in legalizer
New instructions were getting printed both in createdInstr, and in the
final printNewInstrs, so it made it look like the same instructions
were created twice. This overall made reading the debug output
harder. Stop printing the initial construction and only print new
instructions in the summary at the end. This avoids printing the less
useful case where instructions are sometimes initially created with no
operands.

I'm not sure this is the correct instance to remove; now the visible
ordering is different. Now you will typically see the one erased
instruction message before all the new instructions in order. I think
this is the more logical view of typical legalization changes,
although it's mechanically backwards from the normal
insert-new-erase-old pattern.
2020-06-09 15:02:31 -04:00
Mehdi Amini
ed76433842 Change filecheck default to dump input on failure
Having the input dumped on failure seems like a better
default: I debugged FileCheck tests for a while without knowing
about this option, which really helps to understand failures.

Remove `-dump-input-on-failure` and the environment variable
FILECHECK_DUMP_INPUT_ON_FAILURE which are now obsolete.

Differential Revision: https://reviews.llvm.org/D81422
2020-06-09 18:57:46 +00:00
Anh Tuyen Tran
a3bbcd952c [NFC][LV][TEST]: extend pr45679-fold-tail-by-masking.ll with -force-vector-width=1 -force-vector-interleave=4
Summary:
Add -force-vector-width=1 -force-vector-interleave=4 to pr45679-fold-tail-by-masking.ll

Author: anhtuyen (Anh Tuyen Tran)

Reviewers: Ayal (Ayal Zaks)

Reviewed By: Ayal (Ayal Zaks)

Subscribers: rkruppe (Hanna Kruppe), llvm-commits, LLVM

Tag: LLVM

Differential Revision: https://reviews.llvm.org/D80446
2020-06-09 18:30:56 +00:00
David Green
f56c09c87f [MachineScheduler] Update available queue on the first mop of a new cycle
If a resource can be held for multiple cycles in the schedule model
then an instruction can be placed into the available queue, another
instruction can be scheduled, but the first will not be taken back out if
the two instructions hazard. To fix this make sure that we update the
available queue even on the first MOp of a cycle, pushing available
instructions back into the pending queue if they now conflict.

This happens with some downstream schedules we have around MVE
instruction scheduling where we use ResourceCycles=[2] to show the
instruction executing over two beats. Apparently the test changes here
are OK too.

Differential Revision: https://reviews.llvm.org/D76909
2020-06-09 19:13:53 +01:00
Fangrui Song
d2790b14ca [gcov][test] Add mkdir -p %t && cd %t
This allows an alternative lit runner (which does not chdir to %T)
to run within a read-only source tree.
2020-06-09 11:09:50 -07:00
Simon Pilgrim
7cc81c9a51 [VectorCombine] scalarizeBinop - support an all-constant src vector operand
scalarizeBinop currently folds

  vec_bo((inselt VecC0, V0, Index), (inselt VecC1, V1, Index))
  ->
  inselt(vec_bo(VecC0, VecC1), scl_bo(V0,V1), Index)

This patch extends this to account for cases where one of the vec_bo operands is already all-constant and performs similar cost checks to determine if the scalar binop with a constant still makes sense:

  vec_bo((inselt VecC0, V0, Index), VecC1)
  ->
  inselt(vec_bo(VecC0, VecC1), scl_bo(V0,extractelt(V1,Index)), Index)

Fixes PR42174

Differential Revision: https://reviews.llvm.org/D80885
2020-06-09 19:02:05 +01:00
Daniel Kiss
a382f706d9 [AArch64] Allow BTI mnemonics in the HINT space with BTI disabled
Summary:
It is important to emit HINT instructions instead of BTI  ones when
BTI is disabled. This allows compatibility with other assemblers
(e.g. GAS).

Still, developers of assembly code will want to write code that is
compatible with both pre- and post-BTI CPUs. They could use HINT
mnemonics, but the new mnemonics are a lot more readable (e.g.
bti c instead of hint #34), and they will result in the same
encodings. So, while LLVM should not *emit* the new mnemonics when
BTI is disabled, this patch will at least make LLVM *accept*
assembly code that uses them.

Reviewers: pbarrio, tamas.petz, ostannard

Reviewed By: pbarrio, ostannard

Subscribers: ostannard, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81257
2020-06-09 19:57:02 +02:00
Jessica Paquette
aaa8ca2847 [AArch64][GlobalISel] Select trn1 and trn2
Same idea as for zip, uzp, etc. Teach the post-legalizer combiner to recognize
G_SHUFFLE_VECTORs that are trn1/trn2 instructions.

- Add G_TRN1 and G_TRN2
- Port mask matching code from AArch64ISelLowering
- Produce G_TRN1 and G_TRN2 in the post-legalizer combiner
- Select via importer

Add select-trn.mir to test selection.

Add postlegalizer-combiner-trn.mir to test the combine. This is similar to the
existing arm64-trn test.

Note that both of these tests contain things we currently don't legalize.

I figured it would be easier to test these now rather than later, since once
we legalize the G_SHUFFLE_VECTORs, it's not guaranteed that someone will update
the tests.

Differential Revision: https://reviews.llvm.org/D81182
2020-06-09 10:55:19 -07:00
Thomas Lively
e0fb71605e [WebAssembly] Implement prototype SIMD rounding instructions
Summary:
As specified in https://github.com/WebAssembly/simd/pull/232. These
instructions are implemented as LLVM intrinsics for now rather than
normal ISel patterns to make these instructions opt-in. Once the
instructions are merged to the spec proposal, the intrinsics will be
replaced with proper ISel patterns.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D81222
2020-06-09 10:14:14 -07:00
Fangrui Song
a4f74ca229 [DebugInfo] Drop unneeded format() calls (fix -Wformat-security) after 3b7ec64d59748765990ed99716034ab8d5533673 2020-06-09 09:56:13 -07:00
Henry Kao
fb5be176f1 [CodeGen][SVE] Avoid scalarizing zero splat stores on scalable vectors.
Summary: Implemented in replaceZeroVectorStore(). Fixes several warnings in AArch64 SVE unit tests.

Reviewers: sdesmalen, kmclaughlin, dancgr, efriedma, each, andwar, rengolin

Reviewed By: sdesmalen

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80824
2020-06-09 12:52:39 -04:00
Simon Pilgrim
28013357a6 [InstCombine] Ensure allocation alignment mask is within range before applying as an attribute
Fixes OSS-Fuzz #23214
https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=23214
2020-06-09 17:31:55 +01:00
Aaron Puchert
b9b65b60ee Add LLVM_ATTRIBUTE_NORETURN to report_bad_alloc_error
Summary:
The attribute just means that there will be no regular return, it still
leaves room for exceptions to be thrown. It is easily verified: there
are no direct returns and the last statement is either a throw or a call
to abort.

Having the annotation helps static analyzers with this code from
Support/MemAlloc.h (slightly simplified):

LLVM_ATTRIBUTE_RETURNS_NONNULL inline void *safe_malloc(size_t Sz) {
  void *Result = std::malloc(Sz);
  if (Result == nullptr)
    report_bad_alloc_error("Allocation failed");
  return Result;
}

Were report_bad_alloc_error to return regularly, the function would
return nullptr, contradicting the attribute.

Reviewers: rnk, sepavloff, dblaikie, aaron.ballman

Reviewed By: dblaikie, aaron.ballman

Differential Revision: https://reviews.llvm.org/D81318
2020-06-09 17:45:12 +02:00
Xing GUO
f42b0b95f0 [ObjectYAML][ELF] Add support for emitting the .debug_line section.
This patch enables yaml2elf emit the .debug_line section.

Test cases for emitting the dwarf64 .debug_line section and opcodes will be added later.

Known issues:
- We should replace `InitialLength` with `Format` and `Length`
- Currently implementation of the .debug_line section only fully supports DWARFv2, some header fields in DWARFv4 and DWARFv5 is missing, e.g., `header_length` in DWARFv4, `address_size` and `segment_selector_size` in DWARFv5.
- Some opcodes relies on the .debug_info section, we should warn user about it.

These issues will be addressed in a follow-up patch.

Reviewed By: jhenderson, grimar

Differential Revision: https://reviews.llvm.org/D81450
2020-06-09 23:42:40 +08:00
Florian Hahn
fa86d844ec [PatternMatch] Support matching intrinsics with 6 arguments.
I couldn't find a generic intrinsic with 6 arguments in tree for a
unit test, but soon there will be one.
2020-06-09 15:59:26 +01:00
Florian Hahn
e79fa2344f [Matrix] Update check lines for strided intrinsics (NFC).
This re-generates some check lines, after the naming of values got
improved, to reduce the size of diffs in follow-on patches.
2020-06-09 15:51:00 +01:00
Sanjay Patel
2d91437b89 [DAGCombiner] allow more folding of fadd + fmul into fma
If fmul and fadd are separated by an fma, we can fold them together
to save an instruction:
fadd (fma A, B, (fmul C, D)), N1 --> fma(A, B, fma(C, D, N1))

The fold implemented here is actually a specialization - we should
be able to peek through >1 fma to find this pattern. That's another
patch if we want to try that enhancement though.

This transform was guarded by the TLI hook enableAggressiveFMAFusion(),
so it was done for some in-tree targets like PowerPC, but not AArch64
or x86. The hook is protecting against forming a potentially more
expensive computation when fma takes longer to execute than a single
fadd. That hook may be needed for other transforms, but in this case,
we are replacing fmul+fadd with fma, and the fma should never take
longer than the 2 individual instructions.

'contract' FMF is all we need to allow this transform. That flag
corresponds to -ffp-contract=fast in Clang, so we are allowed to form
fma ops freely across expressions.

Differential Revision: https://reviews.llvm.org/D80801
2020-06-09 10:41:27 -04:00
Sanjay Patel
35ac141db8 [x86] add test for constant hoisting of 8-bit immediate; NFC (PR46237) 2020-06-09 10:41:27 -04:00
LLVM GN Syncbot
ca1651bcd8 [gn build] Port 9b02a9b4015 2020-06-09 13:58:14 +00:00
LLVM GN Syncbot
1608fd02d6 [gn build] Port 98db1f990fc 2020-06-09 13:58:13 +00:00
LLVM GN Syncbot
3314f05a68 [gn build] Port 813734dad7e 2020-06-09 13:58:13 +00:00
hsmahesha
81cd0cd18c Revert "[AMDGPU/MemOpsCluster] Implement new heuristic for computing max mem ops cluster size"
This reverts commit 40a632a335119fe3e8d5d500a5d2641998314ecb.
2020-06-09 19:27:17 +05:30
James Henderson
048b365457 [DebugInfo] Fix printing of unrecognised standard opcodes
The verbose printing of unrecognised standard opcodes was broken in
multiple ways (additional blank lines, a closing parenthesis without
opening parenthesis and so on). This patch fixes it, and makes the
output more consistent with other opcodes.
2020-06-09 14:32:20 +01:00
James Henderson
53a244b58c [DebugInfo] Improve new line printing in debug line verbose output
The new line printing for debug line verbose output was inconsistent.
For new rows in the matrix, a blank line followed, whilst the
DW_LNS_copy opcode actually resulted in two blank lines. There was also
potential inconsistency in the blank lines at the end of the table. This
patch mostly resolves these issues - no blank lines appear in the output
except for a single line after the prologue and at table end to separate
it from any subsquent table, plus some instances after error messages.

Also add a unit test for verbose output to test the fine details of new
line placement and other aspects of verbose output.

Reviewed by: dblaikie

Differential Revision: https://reviews.llvm.org/D81102
2020-06-09 14:27:16 +01:00
James Henderson
7c86978535 [DebugInfo] Print non-verbose output at some point as verbose output
Verbose and non-verbose parsing of .debug_line produced their output at
different points in the program. The most obvious impact of this was
that error messages were produced at different times, but it also
potentially reduced what clients could do by customising the stream or
warning/error handlers.

This change makes the two variants consistent by printing non-verbose
output inline, the same as verbose output.

Testing of the error messages has been modified to check the messages
always appear in the same location to illustrate the behaviour.

Reviewed by: JDevlieghere, dblaikie, MaskRay, labath

Differential Revision: https://reviews.llvm.org/D80989
2020-06-09 14:24:53 +01:00
Simon Pilgrim
47b5716c31 Fix Wdocumentation warning. NFC.
The raw unsigned Opc value has been replaced with the ShuffleVectorPseudo MatchInfo wrapper struct.
2020-06-09 13:53:39 +01:00
James Henderson
fd7e7a7ad4 [DebugInfo] Remove unnecessary flushes and add additional testing
The flushes previously existed to help ensure consistent error message
output when stdout and stderr were passed to the same location. This is
no longer necessary as errs() is now tied to outs().

Reviewed by: dblaikie, MaskRay, JDevlieghere, labath

Differential Revision: https://reviews.llvm.org/D80803
2020-06-09 13:50:58 +01:00
Kristof Beyls
cade44f8bc Fix race condition in llvm/test/MC/AArch64/mov-expr* tests
... that were introduced in
https://reviews.llvm.org/rG0e1accd0f726eef2c47be9f37dd0a06cb50d207e
2020-06-09 13:25:09 +01:00
serge-sans-paille
b8f042119c Fix MemCpyOptimizer return status
Differential Revision: https://reviews.llvm.org/D81229
2020-06-09 14:24:33 +02:00
serge-sans-paille
1ca64c17dc Update pass status for GCOVProfiling
Take fork/exec instrumentation into account.

Differential Revision: https://reviews.llvm.org/D81227
2020-06-09 14:23:30 +02:00
Kazushi (Jam) Marukawa
04475a0f09 [VE] Support rest of load/store instructions in MC layer
Summary:
Add DLD/DLDU/DLDL/PFCH/TS1AM/TS2AM/TS3AM/ATMAM/CAS instructions newly.
Add regression tests for them to asmparser, mccodeemitter, and disassembler.
In order to add those instructions, change asmparser to support UImm0to2 and
UImm1 operands, add new decode functions to disassembler, and add new print
functions to instprinter.

Differential Revision: https://reviews.llvm.org/D81454
2020-06-09 14:21:00 +02:00
James Henderson
17d5bec07f [Support] Add stream tie function and use it for errs()
errs() is now tied to outs() so that if something prints to errs(),
outs() will be flushed before the printing occurs. This avoids
interleaving output between the two and is consistent with standard cout
and cerr behaviour.

Reviewed by: labath, JDevlieghere, MaskRay

Differential Revision: https://reviews.llvm.org/D81156
2020-06-09 12:51:02 +01:00
David Green
8a5c6f3865 [ARM] Add some MVE vecreduce tests. NFC 2020-06-09 12:07:19 +01:00
Simon Pilgrim
1b551d1455 [X86][SSE] Add PTEST test cases for PR45378 2020-06-09 11:54:51 +01:00
Simon Pilgrim
c7c985802b Magic.h - reduce includes to forward declarations. NFC. 2020-06-09 11:54:51 +01:00