Dan Gohman
cd25487258
Pool-allocation for MachineInstrs, MachineBasicBlocks, and
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MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
llvm-svn: 53212
2008-07-07 23:14:23 +00:00
Evan Cheng
1f6148a84c
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc.
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- Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list.
llvm-svn: 53097
2008-07-03 09:09:37 +00:00
Dan Gohman
c8097f8c8c
Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
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the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.
Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.
This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.
llvm-svn: 52943
2008-07-01 00:05:16 +00:00
Evan Cheng
2dfe8c2435
Add option to commuteInstruction() which forces it to create a new (commuted) instruction.
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llvm-svn: 52308
2008-06-16 07:33:11 +00:00
Nicolas Geoffray
82baa2d2c6
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
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llvm-svn: 49809
2008-04-16 20:10:13 +00:00
Chris Lattner
6c4486c5c7
detabify llvm, patch by Mike Stump!
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llvm-svn: 48577
2008-03-20 01:22:40 +00:00
Bill Wendling
80bc045af5
Change the "enable/disable" mechanism so that we can enable PPC register
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scavenging for 32-bit and 64-bit separately.
llvm-svn: 48186
2008-03-10 22:49:16 +00:00
Chris Lattner
52be2c645e
fix 80 col violations.
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llvm-svn: 48166
2008-03-10 18:55:53 +00:00
Nicolas Geoffray
a904844534
Stylistic modifications. No functionality changes.
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llvm-svn: 48158
2008-03-10 17:46:45 +00:00
Nicolas Geoffray
e3381f0f1f
Add description of individual bits in CR. This fix PR1765.
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llvm-svn: 48143
2008-03-10 14:12:10 +00:00
Bill Wendling
dc9de245cb
Use a command-line option to turn register scavenging on/off for PPC.
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llvm-svn: 47915
2008-03-04 23:13:51 +00:00
Bill Wendling
8d64999daf
This is the initial check-in for adding register scavenging to PPC. (Currently,
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PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.
llvm-svn: 47863
2008-03-03 22:19:16 +00:00
Evan Cheng
4b37f5ff05
commuteInstr() can now commute non-ssa machine instrs.
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llvm-svn: 47043
2008-02-13 02:46:49 +00:00
Evan Cheng
90f03a0b88
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
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llvm-svn: 46893
2008-02-08 21:20:40 +00:00
Chris Lattner
55343065e3
remove MachineOpCode typedef.
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llvm-svn: 45679
2008-01-07 02:48:55 +00:00
Owen Anderson
f19692b2f6
Move even more functionality from MRegisterInfo into TargetInstrInfo.
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Some day I'll get it all moved over...
llvm-svn: 45672
2008-01-07 01:35:02 +00:00
Owen Anderson
e6856128ab
Move some more instruction creation methods from RegisterInfo into InstrInfo.
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llvm-svn: 45484
2008-01-01 21:11:32 +00:00
Chris Lattner
04a35e9a8c
Fix a bug in my previous patch: refer to the impl not the pure virtual version. It's unclear why gcc would ever compile this...
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llvm-svn: 45476
2008-01-01 01:05:34 +00:00
Chris Lattner
1285ec2ae7
Fix a problem where lib/Target/TargetInstrInfo.h would include and use
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a header file from libcodegen. This violates a layering order: codegen
depends on target, not the other way around. The fix to this is to
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen. It is defined in libcodegen, where
the base is not.
llvm-svn: 45475
2008-01-01 01:03:04 +00:00
Owen Anderson
ae7e2c1e03
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
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Machine-level API cleanup instigated by Chris.
llvm-svn: 45470
2007-12-31 06:32:00 +00:00
Chris Lattner
9e5cc35593
Add new shorter predicates for testing machine operands for various types:
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e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on
switching everything over, so new clients should just start using the
shorter names.
Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(),
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.
llvm-svn: 45464
2007-12-30 23:10:15 +00:00
Chris Lattner
7504adbd72
More cleanups for MachineOperand:
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- Eliminate the static "print" method for operands, moving it
into MachineOperand::print.
- Change various set* methods for register flags to take a bool
for the value to set it to. Remove unset* methods.
- Group methods more logically by operand flavor in MachineOperand.h
llvm-svn: 45461
2007-12-30 21:56:09 +00:00
Chris Lattner
12477d46b4
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
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llvm-svn: 45453
2007-12-30 20:49:49 +00:00
Chris Lattner
ad9a6ccb83
Remove attribution from file headers, per discussion on llvmdev.
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llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Owen Anderson
4b71e55287
Add lengthof and endof templates that hide a lot of sizeof computations.
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Patch by Sterling Stein!
llvm-svn: 41758
2007-09-07 04:06:50 +00:00
Dale Johannesen
7e3253f115
Handle blocks with 2 unconditional branches in AnalyzeBranch.
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llvm-svn: 37571
2007-06-13 17:59:52 +00:00
Evan Cheng
1a6c0341fd
Add a utility routine to check for unpredicated terminator instruction.
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llvm-svn: 37528
2007-06-08 21:59:56 +00:00
Evan Cheng
3f386274c0
BlockHasNoFallThrough() now returns true if block ends with a return instruction.
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llvm-svn: 37266
2007-05-21 18:44:17 +00:00
Evan Cheng
234aab208a
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
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llvm-svn: 37192
2007-05-18 00:05:48 +00:00
Evan Cheng
de9468373e
Relex assertions to account for additional implicit def / use operands.
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llvm-svn: 36430
2007-04-25 07:12:14 +00:00
Bill Wendling
f13d78d3b8
What should be the last unnecessary <iostream>s in the library.
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llvm-svn: 32333
2006-12-07 22:21:48 +00:00
Evan Cheng
98fa7ab4d7
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
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of opcode and number of operands.
llvm-svn: 31947
2006-11-27 23:37:22 +00:00
Chris Lattner
0d88b19f2f
convert PPC::BCC to use the 'pred' operand instead of separate predicate
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value and CR reg #. This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(
llvm-svn: 31835
2006-11-17 22:37:34 +00:00
Chris Lattner
73329ae80d
rename PPC::COND_BRANCH to PPC::BCC
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llvm-svn: 31834
2006-11-17 22:14:47 +00:00
Chris Lattner
1527483a15
start using PPC predicates more consistently.
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llvm-svn: 31833
2006-11-17 22:10:59 +00:00
Evan Cheng
2a92afa25d
Properly transfer kill / dead info.
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llvm-svn: 31765
2006-11-15 20:58:11 +00:00
Evan Cheng
0e82270ff2
Matches MachineInstr changes.
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llvm-svn: 31712
2006-11-13 23:36:35 +00:00
Chris Lattner
a478e05437
implement the BlockHasNoFallThrough hook
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llvm-svn: 31264
2006-10-28 17:35:02 +00:00
Chris Lattner
a9adb1e558
Implement support for branch reversal, fix a bug in branch analysis.
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This provides stuff like:
cmpw cr0, r15, r29
mr r14, r15
- bge cr0, LBB3_111 ;bb656
- b LBB3_90 ;bb501
+ blt cr0, LBB3_90 ;bb501
LBB3_111: ;bb656
lwz r18, 68(r1)
which is particularly good for dispatch group formation.
llvm-svn: 31101
2006-10-21 06:03:11 +00:00
Chris Lattner
20bb8bfd45
Simplify code, no functionality change
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llvm-svn: 31097
2006-10-21 05:42:09 +00:00
Chris Lattner
d3e583b2e1
implement support for inserting a cond branch
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llvm-svn: 31096
2006-10-21 05:36:13 +00:00
Chris Lattner
bf15d2f503
add support for inserting an uncond branch
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llvm-svn: 31003
2006-10-17 18:06:55 +00:00
Chris Lattner
b90d66b7da
implement branch inspection/modification methods.
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llvm-svn: 30946
2006-10-13 21:21:17 +00:00
Chris Lattner
2db97248f8
In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones.
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llvm-svn: 29096
2006-07-11 00:48:23 +00:00
Chris Lattner
75e6449a0f
Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file
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llvm-svn: 28889
2006-06-20 23:18:58 +00:00
Chris Lattner
d817b32a8e
Implement the getPointerRegClass method, which is required for the ptr_rc
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magic to work.
llvm-svn: 28847
2006-06-17 00:01:04 +00:00
Chris Lattner
685568510a
Move some methods out of MachineInstr into MachineOperand
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llvm-svn: 28102
2006-05-04 17:52:23 +00:00
Chris Lattner
57773fdac1
teach the ppc backend how to spill/reload vector regs
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llvm-svn: 26806
2006-03-16 22:24:02 +00:00
Chris Lattner
bf153651b1
Add support for copying registers. still needed: spilling and reloading them
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llvm-svn: 26800
2006-03-16 20:03:58 +00:00
Chris Lattner
af44ead7f3
implement TII::insertNoop
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llvm-svn: 26562
2006-03-05 23:49:55 +00:00