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Commit Graph

4098 Commits

Author SHA1 Message Date
Chris Lattner
0841469ff0 Add a (disabled by default) way to view the ID of a node.
llvm-svn: 42978
2007-10-15 05:32:43 +00:00
Chris Lattner
95def2ca5a remove misleading comment.
llvm-svn: 42970
2007-10-14 20:35:12 +00:00
Chris Lattner
ac17bf4c0f If a target doesn't have HasMULHU or HasUMUL_LOHI, ExpandOp would return
without lo/hi set.  Fall through to making a libcall instead.

llvm-svn: 42969
2007-10-14 18:35:05 +00:00
Evan Cheng
62ee7cd439 When coalescing an EXTRACT_SUBREG and the dst register is a physical register,
the source register will be coalesced to the super register of the LHS. Properly
merge in the live ranges of the resulting coalesced interval that were part of
the original source interval to the live interval of the super-register.

llvm-svn: 42961
2007-10-14 10:08:34 +00:00
Evan Cheng
33df6a6bed Revert 42908 for now.
llvm-svn: 42960
2007-10-14 05:57:21 +00:00
Dale Johannesen
4cbce377c6 Disable some compile-time optimizations on PPC
long double.

llvm-svn: 42958
2007-10-14 01:56:47 +00:00
Chris Lattner
c146f449b5 Enhance the truncstore optimization code to handle shifted
values and propagate demanded bits through them in simple cases.

This allows this code:
void foo(char *P) {
   strcpy(P, "abc");
}
to compile to:

_foo:
        ldrb r3, [r1]
        ldrb r2, [r1, #+1]
        ldrb r12, [r1, #+2]!
        ldrb r1, [r1, #+1]
        strb r1, [r0, #+3]
        strb r2, [r0, #+1]
        strb r12, [r0, #+2]
        strb r3, [r0]
        bx lr

instead of:

_foo:
        ldrb r3, [r1, #+3]
        ldrb r2, [r1, #+2]
        orr r3, r2, r3, lsl #8
        ldrb r2, [r1, #+1]
        ldrb r1, [r1]
        orr r2, r1, r2, lsl #8
        orr r3, r2, r3, lsl #16
        strb r3, [r0]
        mov r2, r3, lsr #24
        strb r2, [r0, #+3]
        mov r2, r3, lsr #16
        strb r2, [r0, #+2]
        mov r3, r3, lsr #8
        strb r3, [r0, #+1]
        bx lr

testcase here: test/CodeGen/ARM/truncstore-dag-combine.ll

This also helps occasionally for X86 and other cases not involving 
unaligned load/stores.

llvm-svn: 42954
2007-10-13 06:58:48 +00:00
Chris Lattner
133baf6012 Add a simple optimization to simplify the input to
truncate and truncstore instructions, based on the 
knowledge that they don't demand the top bits.

llvm-svn: 42952
2007-10-13 06:35:54 +00:00
Evan Cheng
b9ab88ccd5 Local spiller optimization:
Turn this:
movswl  %ax, %eax
movl    %eax, -36(%ebp)
xorl    %edi, -36(%ebp)
into
movswl  %ax, %eax
xorl    %edi, %eax
movl    %eax, -36(%ebp)
by unfolding the load / store xorl into an xorl and a store when we know the
value in the spill slot is available in a register. This doesn't change the
number of instructions but reduce the number of times memory is accessed.

Also unfold some load folding instructions and reuse the value when similar
situation presents itself.

llvm-svn: 42947
2007-10-13 02:50:24 +00:00
Evan Cheng
2262b2a792 Optionally create a MachineInstr without default implicit operands.
llvm-svn: 42945
2007-10-13 02:23:01 +00:00
Arnold Schwaighofer
6bcd9e7ec2 Corrected many typing errors. And removed 'nest' parameter handling
for fastcc from X86CallingConv.td.  This means that nested functions
are not supported for calling convention 'fastcc'.

llvm-svn: 42934
2007-10-12 21:30:57 +00:00
Dale Johannesen
2f62d5da32 ppc long double. Implement fabs and fneg.
llvm-svn: 42924
2007-10-12 19:02:17 +00:00
Dale Johannesen
296cc4ca22 Implement i64->ppcf128 conversions.
llvm-svn: 42919
2007-10-12 17:52:03 +00:00
Evan Cheng
681a96d737 Did mean to leave this in. INSERT_SUBREG isn't being coalesced yet.
llvm-svn: 42916
2007-10-12 17:16:50 +00:00
Dan Gohman
a75e4a62e6 Change the names used for internal labels to use the current
function symbol name instead of a codegen-assigned function
number.

Thanks Evan! :-)

llvm-svn: 42908
2007-10-12 14:53:36 +00:00
Dan Gohman
330b7915da Fix some corner cases with vectors in copyToRegs and copyFromRegs.
llvm-svn: 42907
2007-10-12 14:33:11 +00:00
Dan Gohman
b0b156e238 Add support to SplitVectorOp for powi, where the second operand
is a scalar integer.

llvm-svn: 42906
2007-10-12 14:13:46 +00:00
Evan Cheng
9beb8daf9c Restrict EXTRACT_SUBREG coalescing to avoid negative performance impact.
llvm-svn: 42903
2007-10-12 09:15:53 +00:00
Evan Cheng
d11cd4a095 EXTRACT_SUBREG coalescing support. The coalescer now treats EXTRACT_SUBREG like
(almost) a register copy. However, it always coalesced to the register of the
RHS (the super-register). All uses of the result of a EXTRACT_SUBREG are sub-
register uses which adds subtle complications to load folding, spiller rewrite,
etc.

llvm-svn: 42899
2007-10-12 08:50:34 +00:00
Evan Cheng
8af3000e93 Some clean up.
llvm-svn: 42898
2007-10-12 08:45:27 +00:00
Dale Johannesen
4ade2701e0 PPC long double. Implement a couple more conversions.
llvm-svn: 42888
2007-10-12 01:37:08 +00:00
Dan Gohman
ab5c3ed0d1 Add intrinsics for sin, cos, and pow. These use llvm_anyfloat_ty, and so
may be overloaded with vector types. And add a testcase for codegen for
these.

llvm-svn: 42885
2007-10-12 00:01:22 +00:00
Dan Gohman
b9863c4738 Codegen support for vector intrinsics.
Factor out the code that expands the "nasty scalar code" for unrolling
vectors into a separate routine, teach it how to handle mixed
vector/scalar operands, as seen in powi, and use it for several operators,
including sin, cos, powi, and pow.

Add support in SplitVectorOp for fpow, fpowi and for several unary
operators.

llvm-svn: 42884
2007-10-11 23:57:53 +00:00
Dale Johannesen
781403c410 Implement ppc long double->uint conversion.
Make ppc long double constants print.

llvm-svn: 42882
2007-10-11 23:32:15 +00:00
Dan Gohman
f8ab690988 Add runtime library names for pow.
llvm-svn: 42880
2007-10-11 23:09:10 +00:00
Dan Gohman
bc5fc4f519 Add an ISD::FPOW node type.
llvm-svn: 42879
2007-10-11 23:06:37 +00:00
Arnold Schwaighofer
d47210011e Added tail call optimization to the x86 back end. It can be
enabled by passing -tailcallopt to llc.  The optimization is
performed if the following conditions are satisfied:
* caller/callee are fastcc
* elf/pic is disabled OR
  elf/pic enabled + callee is in module + callee has
  visibility protected or hidden

llvm-svn: 42870
2007-10-11 19:40:01 +00:00
Dale Johannesen
0ee2a2fb59 Next PPC long double bits. First cut at constants.
No compile-time support for constant operations yet,
just format transformations.  Make readers and
writers work.  Split constants into 2 doubles in
Legalize.

llvm-svn: 42865
2007-10-11 18:07:22 +00:00
Duncan Sands
a8baeb6dab Correct swapped arguments to getConstant.
llvm-svn: 42824
2007-10-10 09:54:50 +00:00
Dale Johannesen
76458ddf1e Next PPC long double bits: ppcf128->i32 conversion.
Surprisingly complicated.
Adds getTargetNode for 2 outputs, no inputs (missing).

llvm-svn: 42822
2007-10-10 01:01:31 +00:00
Evan Cheng
726b00c4dd Bad choice of variable name.
llvm-svn: 42821
2007-10-10 00:11:40 +00:00
Evan Cheng
f979e5b206 Fix an extremely stupid bug that prevented first round of coalescing (physical registers only) from happening.
llvm-svn: 42820
2007-10-09 23:36:27 +00:00
Dan Gohman
f8c79a885f Call getFunctionNumber() instead of referencing FunctionNumber directly,
for consistency.

llvm-svn: 42769
2007-10-08 21:27:12 +00:00
Dan Gohman
6df332f0cb Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.

llvm-svn: 42762
2007-10-08 18:33:35 +00:00
Dan Gohman
6f2a2b45fa DAGCombiner support for UDIVREM/SDIVREM and UMUL_LOHI/SMUL_LOHI.
Check if one of the two results unneeded so see if a simpler operator
could bs used. Also check to see if each of the two computations could be
simplified if they were split into separate operators. Factor out the code
that calls visit() so that it can be used for this purpose.

llvm-svn: 42759
2007-10-08 17:57:15 +00:00
Dan Gohman
9ee1c4eee7 Add convenience overloads of SelectionDAG::getNode that take a SDVTList
and individual SDOperand operands.

llvm-svn: 42753
2007-10-08 15:49:58 +00:00
Dan Gohman
58512cb6e2 In -debug mode, dump SelectionDAGs both before and after the
optimization passes.

llvm-svn: 42749
2007-10-08 15:12:17 +00:00
Evan Cheng
96099de5bb Kill cycle of an live range is always the last use index + 1.
llvm-svn: 42742
2007-10-08 06:59:30 +00:00
Neil Booth
6e01c5df37 convertFromInteger, as originally written, expected sign-extended
input.  APInt unfortunately zero-extends signed integers, so Dale
modified the function to expect zero-extended input.  Make this
assumption explicit in the function name.

llvm-svn: 42732
2007-10-07 11:45:55 +00:00
Evan Cheng
0eed7948ce Reapply 42677.
llvm-svn: 42692
2007-10-06 08:19:55 +00:00
Chris Lattner
63443a5bc3 revert evan's patch until the header is committed
llvm-svn: 42686
2007-10-06 06:08:17 +00:00
Evan Cheng
dc95020e30 Added DAG xforms. e.g.
(vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) 
(vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
Remove x86 specific patterns.

llvm-svn: 42677
2007-10-06 02:46:29 +00:00
Dale Johannesen
9b7ac95116 Next powerpc long double bits. Comparisons work,
although not well, and shortening FP converts.

llvm-svn: 42672
2007-10-06 01:24:11 +00:00
Dale Johannesen
c7b51b678d First round of ppc long double. call/return and
basic arithmetic works.
Rename RTLIB long double functions to distinguish
different flavors of long double; the lib functions
have different names, alas.

llvm-svn: 42644
2007-10-05 20:04:43 +00:00
Dan Gohman
06e6956edb Legalize support for MUL_LOHI and DIVREM.
llvm-svn: 42636
2007-10-05 14:17:22 +00:00
Dan Gohman
6132098d91 Fix a typo in a comment.
llvm-svn: 42635
2007-10-05 14:11:58 +00:00
Dan Gohman
dab5fa8685 Provide names for MUL_LOHI and DIVREM operators.
llvm-svn: 42634
2007-10-05 14:11:04 +00:00
Evan Cheng
ed7614b4d6 Chain producing nodes cannot be moved, not chain reading nodes.
llvm-svn: 42627
2007-10-05 01:42:35 +00:00
Evan Cheng
20239e9725 Oops. Didn't mean to leave this in.
llvm-svn: 42626
2007-10-05 01:39:40 +00:00
Evan Cheng
de07843bf3 If a node that defines a physical register that is expensive to copy. The
scheduler will try a number of tricks in order to avoid generating the
copies. This may not be possible in case the node produces a chain value
that prevent movement. Try unfolding the load from the node before to allow
it to be moved / cloned.

llvm-svn: 42625
2007-10-05 01:39:18 +00:00