Venkatraman Govindaraju
bc8be24d6c
[Sparc] Rewrite MBB's live-in registers for leaf functions. Also, add
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register i7 as a live-in if current function's return address is taken.
This revision fixes PR16269.
llvm-svn: 187433
2013-07-30 19:53:10 +00:00
Venkatraman Govindaraju
a1da2b1b3a
[Sparc] Use call's debugloc for the unimp instruction.
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llvm-svn: 187402
2013-07-30 02:26:29 +00:00
Craig Topper
58fa7a9b4a
Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
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llvm-svn: 186274
2013-07-14 04:42:23 +00:00
Venkatraman Govindaraju
9841400828
[Sparc]: Add memory operands for the frame references in the storeRegToStackSlot
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and loadRegFromStackSlot.
llvm-svn: 184935
2013-06-26 12:40:16 +00:00
Chad Rosier
d00211e479
The getRegForInlineAsmConstraint function should only accept MVT value types.
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llvm-svn: 184642
2013-06-22 18:37:38 +00:00
Bill Wendling
a9576dc938
Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
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llvm-svn: 184360
2013-06-19 21:36:55 +00:00
David Blaikie
813e6b3974
DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
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Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.
llvm-svn: 184067
2013-06-16 20:34:27 +00:00
Venkatraman Govindaraju
9767317993
[Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend.
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llvm-svn: 183613
2013-06-08 15:32:59 +00:00
Jakob Stoklund Olesen
338e393db3
Remember the anyext patterns.
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llvm-svn: 183589
2013-06-07 22:59:29 +00:00
Jakob Stoklund Olesen
3a549110cd
Add missing zextloadi1 to i64 patterns. PR16721.
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llvm-svn: 183587
2013-06-07 22:55:05 +00:00
Bill Wendling
ec5227fffd
Don't cache the instruction and register info from the TargetMachine, because
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the internals of TargetMachine could change.
No functionality change intended.
llvm-svn: 183565
2013-06-07 20:35:25 +00:00
Roman Divacky
8439b144e6
Fix a typo in asm string of BP* family of instructions. With this fix
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I am able to compile/assemble/link/run /bin/echo from FreeBSD.
llvm-svn: 183537
2013-06-07 17:46:57 +00:00
Venkatraman Govindaraju
867986b1ff
[Sparc]: Use cmp instruction instead of subcc to compare integers.
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llvm-svn: 183463
2013-06-07 00:03:36 +00:00
Bill Wendling
2cca7e5acd
Cache the TargetLowering info object as a pointer.
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Caching it as a pointer allows us to reset it if the TargetMachine object
changes.
llvm-svn: 183361
2013-06-06 00:43:09 +00:00
Venkatraman Govindaraju
a65d380b15
Sparc: No functionality change. Cleanup whitespaces, comment formatting etc.,
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llvm-svn: 183243
2013-06-04 18:33:25 +00:00
Venkatraman Govindaraju
2d5d39937e
Sparc: Add support for indirect branch and blockaddress in Sparc backend.
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llvm-svn: 183094
2013-06-03 05:58:33 +00:00
Venkatraman Govindaraju
b47bd839e0
Sparc: When storing 0, use %g0 directly in the store instruction instead of
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using two instructions (sethi and store).
llvm-svn: 183090
2013-06-03 00:21:54 +00:00
Venkatraman Govindaraju
0514a4c845
Sparc: Combine add/or/sethi instruction with restore if possible.
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llvm-svn: 183088
2013-06-02 21:48:17 +00:00
Venkatraman Govindaraju
acb910b7ae
Sparc: Perform leaf procedure optimization by default
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llvm-svn: 183083
2013-06-02 02:24:27 +00:00
Venkatraman Govindaraju
2425aef2ad
Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics as non-leaf functions.
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llvm-svn: 183079
2013-06-01 20:42:48 +00:00
Venkatraman Govindaraju
1eaf496598
[Sparc] Generate correct code for leaf functions with stack objects
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llvm-svn: 183067
2013-06-01 04:51:18 +00:00
Ahmed Bougacha
2263547c8f
Make SubRegIndex size mandatory, following r183020.
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This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.
llvm-svn: 183061
2013-05-31 23:45:26 +00:00
Andrew Trick
aec414c298
Order CALLSEQ_START and CALLSEQ_END nodes.
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Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.
Patch by Xiaoyi Guo!
This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.
llvm-svn: 182885
2013-05-29 22:03:55 +00:00
NAKAMURA Takumi
6eb30bda4d
SparcFrameLowering.cpp: Mark verifyLeafProcRegUse() as UNUSED. [-Wunused-function]
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llvm-svn: 182850
2013-05-29 12:10:42 +00:00
Venkatraman Govindaraju
cb40ce1f29
[Sparc] Add support for leaf functions in sparc backend.
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llvm-svn: 182822
2013-05-29 04:46:31 +00:00
Andrew Trick
2790ee3a8e
Track IR ordering of SelectionDAG nodes 2/4.
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Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
llvm-svn: 182703
2013-05-25 02:42:55 +00:00
Jakob Stoklund Olesen
dad0022424
Also expand 64-bit bitcasts.
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llvm-svn: 182229
2013-05-20 01:01:43 +00:00
Jakob Stoklund Olesen
e033165fd4
Implement spill and fill of I64Regs.
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llvm-svn: 182228
2013-05-20 00:53:25 +00:00
Jakob Stoklund Olesen
f777e6d131
Mark i64 SETCC as expand so it is turned into a SELECT_CC.
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llvm-svn: 182227
2013-05-20 00:28:36 +00:00
Jakob Stoklund Olesen
50d419ac93
Don't use %g0 to materialize 0 directly.
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The wired physreg doesn't work on tied operands like on MOVXCC.
Add a README note to fix this later.
llvm-svn: 182225
2013-05-19 21:47:13 +00:00
Jakob Stoklund Olesen
f4ec84c2d4
Select i64 values with %icc conditions.
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llvm-svn: 182224
2013-05-19 20:38:21 +00:00
Jakob Stoklund Olesen
1948cf9ca7
Add floating point selects on %xcc predicates.
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llvm-svn: 182222
2013-05-19 20:33:11 +00:00
Jakob Stoklund Olesen
c53b3587a3
Implement SPselectfcc for i64 operands.
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Also clean up the arguments to all the MOVCC instructions so the
operands always are (true-val, false-val, cond-code).
llvm-svn: 182221
2013-05-19 20:20:54 +00:00
Venkatraman Govindaraju
d432ed013f
[Sparc] Rearrange integer registers' allocation order so that register allocator will use I and G registers before using L and O registers.
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Also, enable registers %g2-%g4 to be used in application and %g5 in 64 bit mode.
llvm-svn: 182219
2013-05-19 20:07:20 +00:00
Jakob Stoklund Olesen
702a7c68c9
Handle i64 FrameIndex nodes in SPARC v9 mode.
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llvm-svn: 182216
2013-05-19 19:14:24 +00:00
Venkatraman Govindaraju
989fb74a1c
[Sparc] Implements hasReservedCallFrame and hasFP.
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This is to generate correct framesetup code when the function
has variable sized allocas.
llvm-svn: 182108
2013-05-17 15:14:34 +00:00
Venkatraman Govindaraju
62af2fad30
[Sparc] Prevent instructions that defines or uses %o7 to be in call's delay slot.
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llvm-svn: 182063
2013-05-16 23:53:29 +00:00
Rafael Espindola
237980d752
Remove the MachineMove class.
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It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.
I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.
llvm-svn: 181680
2013-05-13 01:16:13 +00:00
Rafael Espindola
d05c5e1727
Remove unused argument.
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llvm-svn: 181618
2013-05-10 18:16:59 +00:00
Jakob Stoklund Olesen
c9f30e9065
Passing arguments to varags functions under the SPARC v9 ABI.
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Arguments after the fixed arguments never use the floating point
registers.
llvm-svn: 179987
2013-04-21 21:36:49 +00:00
Jakob Stoklund Olesen
d8a2b84611
Fix the SETHIimm pattern for 64-bit code.
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Don't ignore the high 32 bits of the immediate.
llvm-svn: 179985
2013-04-21 21:18:03 +00:00
Jakob Stoklund Olesen
cbfbef04da
Compile varargs functions for SPARCv9.
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With a little help from the frontend, it looks like the standard va_*
intrinsics can do the job.
Also clean up an old bitcast hack in LowerVAARG that dealt with
unaligned double loads. Load SDNodes can specify an alignment now.
Still missing: Calling varargs functions with float arguments.
llvm-svn: 179961
2013-04-20 22:49:16 +00:00
Tim Northover
d12b2f24c8
Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.
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llvm-svn: 179939
2013-04-20 12:32:17 +00:00
Jakob Stoklund Olesen
b4edc00933
Add 64-bit multiply and divide instructions for SPARC v9.
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llvm-svn: 179582
2013-04-16 02:57:02 +00:00
Jakob Stoklund Olesen
3b790b7f2e
Use i32 for all SPARC shift amounts, even in 64-bit mode.
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Test case by llvm-stress.
llvm-svn: 179477
2013-04-14 05:48:50 +00:00
Jakob Stoklund Olesen
8fafe8cd31
Add support for the abs64 SPARC v9 code model.
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For when 16 TB just isn't enough.
llvm-svn: 179474
2013-04-14 05:10:36 +00:00
Jakob Stoklund Olesen
d29f125f5b
Add support for the SPARC v9 abs44 code model.
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This is the default model for non-PIC 64-bit code. It supports
text+data+bss linked anywhere in the low 16 TB of the address space.
llvm-svn: 179473
2013-04-14 04:57:51 +00:00
Jakob Stoklund Olesen
c97ab7209a
Use target flags for printing SPARC asm operands.
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64-bit code models need multiple relocations that can't be inferred from
the opcode like they can in 32-bit code.
llvm-svn: 179472
2013-04-14 04:35:19 +00:00
Jakob Stoklund Olesen
b5173ad8fb
Also put target flags on SPARC constant pool references.
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Constant pool entries are accessed exactly the same way as global
variables.
llvm-svn: 179471
2013-04-14 04:35:16 +00:00
Jakob Stoklund Olesen
c23fada5f9
Fix patterns for 64-bit pointers.
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This fixes the pic32 code model for SPARC v9.
llvm-svn: 179469
2013-04-14 01:53:23 +00:00