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22 Commits

Author SHA1 Message Date
Eric Christopher
67c04e77e5 Have MachineFunction cache a pointer to the subtarget to make lookups 
shorter/easier and have the DAG use that to do the same lookup. This
can be used in the future for TargetMachine based caching lookups from
the MachineFunction easily.

Update the MIPS subtarget switching machinery to update this pointer
at the same time it runs.

llvm-svn: 214838
 2014-08-05 02:39:49 +00:00
Eric Christopher
99307e99a2 Remove the TargetMachine forwards for TargetSubtargetInfo based 
information and update all callers. No functional change.

llvm-svn: 214781
 2014-08-04 21:25:23 +00:00
Craig Topper
9900b9f93b [C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. R600 edition 
llvm-svn: 207503
 2014-04-29 07:57:24 +00:00
Craig Topper
6d411cb95a [C++] Use 'nullptr'. Target edition. 
llvm-svn: 207197
 2014-04-25 05:30:21 +00:00
Chandler Carruth
ae889a5f85 [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE 
definition below all of the header #include lines, lib/Target/...
edition.

llvm-svn: 206842
 2014-04-22 02:41:26 +00:00
Owen Anderson
e541764c5f Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changing 
operator* on the by-operand iterators to return a MachineOperand& rather than
a MachineInstr&.  At this point they almost behave like normal iterators!

Again, this requires making some existing loops more verbose, but should pave
the way for the big range-based for-loop cleanups in the future.

llvm-svn: 203865
 2014-03-13 23:12:04 +00:00
Chandler Carruth
87f14b4eec Re-sort all of the includes with ./utils/sort_includes.py so that 
subsequent changes are easier to review. About to fix some layering
issues, and wanted to separate out the necessary churn.

Also comment and sink the include of "Windows.h" in three .inc files to
match the usage in Memory.inc.

llvm-svn: 198685
 2014-01-07 11:48:04 +00:00
Matt Arsenault
9db19365b4 Use llvm_unreachable instead of assert(0) 
llvm-svn: 196971
 2013-12-10 21:37:42 +00:00
Tom Stellard
9da87c6553 R600: Enable folding of inline literals into REQ_SEQUENCE instructions 
Tested-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 188517
 2013-08-16 01:11:55 +00:00
Vincent Lejeune
7266deac85 R600: Do not mergevector after a vector reg is used 
If we merge vector when a vector is used, it will generate an artificial
antidependency that can prevent 2 tex/vtx instructions to use the same
clause and thus generate extra clauses that reduce performance.

There is no test case as such situation is really hard to predict.

llvm-svn: 187516
 2013-07-31 19:32:12 +00:00
Vincent Lejeune
48ea85c102 R600: Fix wrong export reswizzling 
llvm-svn: 185941
 2013-07-09 15:03:19 +00:00
Bill Wendling
aa15a56463 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183561
 2013-06-07 20:28:55 +00:00
Benjamin Kramer
ed67a770b9 Vincent says the element is at most once in the vector, so we don't need a full std::remove. 
llvm-svn: 183541
 2013-06-07 18:18:12 +00:00
Benjamin Kramer
0c09c2c229 R600: Fix a potential iterator invalidation issue. 
As a bonus this reduces the loop from O(n^2) to O(n).

llvm-svn: 183532
 2013-06-07 16:13:49 +00:00
Vincent Lejeune
016ed40e3b R600: Remove an extra break in R600OptimizeVectorRegisters.cpp 
llvm-svn: 183528
 2013-06-07 15:44:53 +00:00
Vincent Lejeune
aeaa3d375a R600: Rewrite an awkward loop in R600MachineScheduler 
llvm-svn: 183458
 2013-06-06 23:08:32 +00:00
NAKAMURA Takumi
230c4940c2 R600OptimizeVectorRegisters.cpp: Tweak a warning. [-Wsometimes-uninitialized] 
FIXME: Is it false alarm?
llvm-svn: 183371
 2013-06-06 02:15:12 +00:00
NAKAMURA Takumi
7d98129541 R600OptimizeVectorRegisters.cpp: Suppress a warning. [-Wunused-variable] 
llvm-svn: 183370
 2013-06-06 02:15:06 +00:00
NAKAMURA Takumi
3381a4cf72 Trailing linefeed. 
llvm-svn: 183369
 2013-06-06 02:15:00 +00:00
Vincent Lejeune
dd2a468cbd R600: Add a pass that merge Vector Register 
Previously commited @183279 but tests were failing, reverted @183286
It was broken because @183336 was missing, now it's there.

llvm-svn: 183343
 2013-06-05 21:38:04 +00:00
Rafael Espindola
f5e919b2e6 Revert "R600: Add a pass that merge Vector Register" 
This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing.

llvm-svn: 183286
 2013-06-05 01:48:30 +00:00
Vincent Lejeune
57d56af481 R600: Add a pass that merge Vector Register 
llvm-svn: 183279
 2013-06-04 23:17:26 +00:00