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5 Commits

Author SHA1 Message Date
Andrew Trick
d09b64fc25 Instruction scheduling itinerary for Intel Atom. 
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.

Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.

Adds a test to verify that the scheduler is working.

Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.

Patch by Preston Gurd!

llvm-svn: 149558
 2012-02-01 23:20:51 +00:00
NAKAMURA Takumi
71c80e7fe7 llvm/test/CodeGen/X86/zext-fold.ll: Relax an expression in stack offset. 
llvm-svn: 147928
 2012-01-11 07:34:22 +00:00
Nick Lewycky
ba962a7115 There's no need to be so picky about the particular register. 
llvm-svn: 133189
 2011-06-16 21:00:00 +00:00
Nick Lewycky
c62f935caf Commit the right set of tests for r133124. Sorry 'bout that! 
llvm-svn: 133133
 2011-06-16 01:35:45 +00:00
Nick Lewycky
f4886c7374 Add a DAGCombine for (ext (binop (load x), cst)). 
llvm-svn: 133124
 2011-06-16 01:15:49 +00:00