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119 Commits

Author SHA1 Message Date
Jim Grosbach
c2c7753f15 add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH 
to update the jmpbuf in the presence of VLAs.

llvm-svn: 104862
 2010-05-27 18:23:48 +00:00
Jim Grosbach
bb4860d2a2 Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in 
ISD::. No functional change.

llvm-svn: 104734
 2010-05-26 20:22:18 +00:00
Evan Cheng
241d2c434e Implement @llvm.returnaddress. rdar://8015977. 
llvm-svn: 104421
 2010-05-22 01:47:14 +00:00
Jim Grosbach
b6cc69c655 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. 
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

llvm-svn: 104419
 2010-05-22 01:06:18 +00:00
Evan Cheng
b5de7de4ce Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode. 
llvm-svn: 104293
 2010-05-20 23:26:43 +00:00
Evan Cheng
85497bd415 Allow TargetLowering::getRegClassFor() to be called on illegal types. Also 
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.

llvm-svn: 103854
 2010-05-15 02:18:07 +00:00
Dan Gohman
fb6f4da0e0 Implement a bunch more TargetSelectionDAGInfo infrastructure. 
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.

llvm-svn: 103481
 2010-05-11 17:31:57 +00:00
Dan Gohman
eaacb8cb1f Remove the TargetLowering::getSubtarget() virtual function, which 
was unused. TargetMachine::getSubtarget() is used instead.

llvm-svn: 103474
 2010-05-11 16:21:03 +00:00
Dan Gohman
68f04d06c8 Get rid of the EdgeMapping map. Instead, just check for BasicBlock 
changes before doing phi lowering for switches.

llvm-svn: 102809
 2010-05-01 00:01:06 +00:00
Dan Gohman
a0f855157e Use const qualifiers with TargetLowering. This eliminates several 
const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.

llvm-svn: 101635
 2010-04-17 15:26:15 +00:00
Dan Gohman
5c8db5ab3f Move per-function state out of TargetLowering subclasses and into 
MachineFunctionInfo subclasses.

llvm-svn: 101634
 2010-04-17 14:41:14 +00:00
Mon P Wang
484bbe6aa9 Reapply address space patch after fixing an issue in MemCopyOptimizer. 
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)

llvm-svn: 100304
 2010-04-04 03:10:48 +00:00
Mon P Wang
0ccf050ca3 Revert r100191 since it breaks objc in clang 
llvm-svn: 100199
 2010-04-02 18:43:02 +00:00
Mon P Wang
a01350755e Reapply address space patch after fixing an issue in MemCopyOptimizer. 
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)

llvm-svn: 100191
 2010-04-02 18:04:15 +00:00
Bob Wilson
aae933cc81 Revert Mon Ping's change 99928, since it broke all the llvm-gcc buildbots. 
llvm-svn: 99948
 2010-03-30 22:27:04 +00:00
Mon P Wang
9351ea594a Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset, 
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
A update of langref will occur in a subsequent checkin.

llvm-svn: 99928
 2010-03-30 20:55:56 +00:00
Bob Wilson
9501c478f7 Revert this change, since it was causing ARM performance regressions. 
--- Reverse-merging r98889 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMISelLowering.h
U    lib/Target/ARM/ARMInstrInfo.td
U    lib/Target/ARM/ARMInstrVFP.td
U    lib/Target/ARM/ARMISelLowering.cpp
U    lib/Target/ARM/ARMInstrFormats.td

llvm-svn: 99010
 2010-03-19 22:51:32 +00:00
Anton Korobeynikov
eeae840ed7 Get rid of target-specific fp <-> int nodes when still I'm here. 
llvm-svn: 98889
 2010-03-18 22:35:45 +00:00
Anton Korobeynikov
23c07f492e Get rid of target-specific nodes for fp16 <-> fp32 conversion. 
llvm-svn: 98888
 2010-03-18 22:35:37 +00:00
Anton Korobeynikov
48357cdc62 Add codegen support for FP16 on ARM 
llvm-svn: 98502
 2010-03-14 18:42:31 +00:00
Bob Wilson
84fc0200bd Use NEON vmin/vmax instructions for floating-point selects. 
Radar 7461718.

llvm-svn: 96572
 2010-02-18 06:05:53 +00:00
Jim Grosbach
a7e098af3b tighten up eh.setjmp sequence a bit. 
llvm-svn: 95603
 2010-02-08 23:22:00 +00:00
Evan Cheng
9057fea7ef Revert 95130. 
llvm-svn: 95160
 2010-02-02 23:55:14 +00:00
Evan Cheng
48375fbf4f Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility. 
llvm-svn: 95130
 2010-02-02 21:29:10 +00:00
Evan Cheng
237629e476 Eliminate target hook IsEligibleForTailCallOptimization. 
Target independent isel should always pass along the "tail call" property. Change
target hook LowerCall's parameter "isTailCall" into a refernce. If the target
decides it's impossible to honor the tail call request, it should set isTailCall
to false to make target independent isel happy.

llvm-svn: 94626
 2010-01-27 00:07:07 +00:00
Jim Grosbach
70af2216fd Patch by David Conrad: 
"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
 sequence it is now."

llvm-svn: 93758
 2010-01-18 19:58:49 +00:00
Jim Grosbach
187ad02a4f Framework for atomic binary operations. The emitter for the pseudo instructions 
just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.

llvm-svn: 91200
 2009-12-12 01:40:06 +00:00
Jim Grosbach
5a1c16e5bb Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in progress. 
llvm-svn: 91090
 2009-12-11 01:42:04 +00:00
Jim Grosbach
be89da9845 Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics. 
llvm-svn: 91003
 2009-12-10 00:11:09 +00:00
Evan Cheng
af90768b3c isLegalICmpImmediate should take a signed integer; code clean up. 
llvm-svn: 86964
 2009-11-12 07:13:11 +00:00
Evan Cheng
a11308742c Add TargetLowering::isLegalICmpImmediate. It tells LSR what immediate can be folded into target icmp instructions. 
llvm-svn: 86858
 2009-11-11 19:05:52 +00:00
Jim Grosbach
ea6c9c17f5 Use Unified Assembly Syntax for the ARM backend. 
llvm-svn: 86494
 2009-11-09 00:11:35 +00:00
Bob Wilson
95064e348a Add ARM codegen for indirect branches. 
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)

llvm-svn: 85577
 2009-10-30 05:45:42 +00:00
Evan Cheng
1babe43881 Use fconsts and fconstd to materialize small fp constants. 
llvm-svn: 85362
 2009-10-28 01:44:26 +00:00
Anton Korobeynikov
829a3a18d2 ARM does not support offset folding (yet). Disable it for now. 
This fixes PR5031. Unfortunately, there is no small testcase :(

llvm-svn: 82643
 2009-09-23 19:04:09 +00:00
Evan Cheng
7cb9c456e5 Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes. 
Not functionality change yet.

llvm-svn: 82273
 2009-09-18 21:02:19 +00:00
Sandeep Patel
9c4e094e2a Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson. 
llvm-svn: 80773
 2009-09-02 08:44:58 +00:00
Bob Wilson
5240e9de02 Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations. 
The instructions can be selected directly from the intrinsics.  We will need
to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but
those are not yet implemented.

llvm-svn: 80117
 2009-08-26 17:39:53 +00:00
Bob Wilson
6d4400e852 Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations, 
now using shuffles instead of intrinsics.

llvm-svn: 79673
 2009-08-21 20:54:19 +00:00
Anton Korobeynikov
20d832fa1b Fix some typos and use type-based isel for VZIP/VUZP/VTRN 
llvm-svn: 79625
 2009-08-21 12:41:42 +00:00
Anton Korobeynikov
218db4a01c Add lowering of ARM 4-element shuffles to multiple instructios via perfectshuffle-generated table. 
llvm-svn: 79624
 2009-08-21 12:41:24 +00:00
Anton Korobeynikov
a2e4bc2312 Use masks not nodes for vector shuffle predicates. Provide set of 'legal' masks, so legalizer won't infinite cycle 
llvm-svn: 79619
 2009-08-21 12:40:07 +00:00
Bob Wilson
fae9057bf0 Add support for Neon VEXT (vector extract) shuffles. 
This is derived from a patch by Anton Korzh.  I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.

llvm-svn: 79428
 2009-08-19 17:03:43 +00:00
Bill Wendling
962adec4ee Reapply r79127. It was fixed by d0k. 
llvm-svn: 79136
 2009-08-15 21:21:19 +00:00
Bill Wendling
bfebbb6477 Revert r79127. It was causing compilation errors. 
llvm-svn: 79135
 2009-08-15 21:14:01 +00:00
Evan Cheng
5d841097a9 Change allowsUnalignedMemoryAccesses to take type argument since some targets 
support unaligned mem access only for certain types. (Should it be size
instead?)

ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.

llvm-svn: 79127
 2009-08-15 19:23:44 +00:00
Evan Cheng
67fd47b38b Add Thumb2 lsr hooks. 
llvm-svn: 79032
 2009-08-14 20:09:37 +00:00
Bob Wilson
d337cde6e5 Create a new ARM-specific DAG node, VDUP, to represent a splat from a 
scalar_to_vector.  Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.

llvm-svn: 78994
 2009-08-14 05:13:08 +00:00
Bob Wilson
7a311914ab During legalization, change Neon vdup_lane operations from shuffles to 
target-specific VDUPLANE nodes.  This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.

llvm-svn: 78993
 2009-08-14 05:08:32 +00:00
Bob Wilson
8cb7da85e3 Revert r78852 for now. I want to do this differently, but I don't have time 
to fix it tonight.

llvm-svn: 78896
 2009-08-13 05:58:56 +00:00