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116 Commits

Author SHA1 Message Date
Roman Divacky
f028b1614b Stack alignment is 16 bytes on FreeBSD/i386 too. 
llvm-svn: 126226
 2011-02-22 17:30:05 +00:00
Duncan Sands
77c058dc70 The stack should be 16 byte aligned on 32 bit solaris. Patch by Yuri. 
llvm-svn: 126130
 2011-02-21 17:37:17 +00:00
NAKAMURA Takumi
00228d0c2c Triple::MinGW64 is deprecated and removed. We can use Triple::MinGW32 generally. 
No one uses *-mingw64. mingw-w64 is represented as {i686|x86_64}-w64-mingw32. In llvm side, i686 and x64 can be treated as similar way.

llvm-svn: 125747
 2011-02-17 12:24:17 +00:00
NAKAMURA Takumi
8d39c3a632 Fix whitespace. 
llvm-svn: 125746
 2011-02-17 12:23:50 +00:00
Evan Cheng
0e8c521bbd Patches to build EFI with Clang/LLVM. By Carl Norum. 
llvm-svn: 124639
 2011-02-01 01:14:13 +00:00
Nate Begeman
cb6d1c8193 Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. 
llvm-svn: 121439
 2010-12-10 00:26:57 +00:00
Benjamin Kramer
851691ddb2 Add patterns for the x86 popcnt instruction. 
- Also adds a new POPCNT subtarget feature that is currently enabled if the target
  supports SSE4.2 (nehalem) or SSE4A (barcelona).

llvm-svn: 120917
 2010-12-04 20:32:23 +00:00
Rafael Espindola
49d508fd19 Jim Asked us to move DataLayout on ARM back to the most specialized classes. Do 
so and also change X86 for consistency.

Investigating if this can be improved a bit.

llvm-svn: 115469
 2010-10-03 18:59:45 +00:00
NAKAMURA Takumi
a4a0276d4f X86Subtarget.h: Fix Cygwin's TD. 
llvm-svn: 114297
 2010-09-18 19:50:42 +00:00
Anton Korobeynikov
32cecc0ecc Properly emit __chkstk call instead of __alloca on non-mingw windows targets. 
Patch by Cameron Esfahani!

llvm-svn: 112902
 2010-09-02 23:03:46 +00:00
Bruno Cardoso Lopes
b034ffa291 Add x86 CLMUL (Carry-less multiplication) cpu feature 
llvm-svn: 109206
 2010-07-23 01:17:51 +00:00
Eric Christopher
f1bb5da020 Have the X86 backend use Triple instead of a string and some enums. 
llvm-svn: 107625
 2010-07-05 19:26:33 +00:00
Dan Gohman
ba64544096 FastISel doesn't yet handle callee-pop functions. 
To support this, move IsCalleePop from X86ISelLowering to X86Subtarget.

llvm-svn: 104866
 2010-05-27 18:43:40 +00:00
Evan Cheng
d4fe387eb8 Enable i16 to i32 promotion by default. 
llvm-svn: 102493
 2010-04-28 08:30:49 +00:00
Evan Cheng
0f4671b0dd isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted. 
llvm-svn: 101979
 2010-04-21 01:47:12 +00:00
Eric Christopher
bbf4e35cf6 Separate out the AES-NI instructions from the SSE4.2 instructions. Add 
a new subtarget option for AES and check for the support.  Add "westmere"
line of processors and add AES-NI support to the core i7.

Add a couple of TODOs for information I couldn't verify.

llvm-svn: 100231
 2010-04-02 21:54:27 +00:00
Evan Cheng
e60ac0f6a6 Nehalem unaligned memory access is fast. 
llvm-svn: 100089
 2010-04-01 05:58:17 +00:00
Evan Cheng
5ace6fffac Turning off post-ra scheduling for x86. It isn't a consistent win. 
llvm-svn: 98810
 2010-03-18 06:55:42 +00:00
Chris Lattner
1469c1b01e add support for pentium class CPUs which do not have cmov, 
PR4841.  Patch by Craig Smith!

llvm-svn: 98496
 2010-03-14 18:31:44 +00:00
Mikhail Glushenkov
47b3719d4b 80-col violations/trailing whitespace. 
llvm-svn: 97427
 2010-02-28 22:54:30 +00:00
Anton Korobeynikov
ffbf0f7027 Setup correct data layout to match gcc's expectations on mingw32. 
llvm-svn: 95981
 2010-02-12 15:28:56 +00:00
Duncan Sands
1c71358944 Fix typo. 
llvm-svn: 93235
 2010-01-12 08:30:46 +00:00
Duncan Sands
f558d05561 Tweak commit 91745, which changed target data for both Mingw and Cygwin, 
to not touch Cygwin: the change caused llvm-gcc build failures due to
long double getting the wrong size.  Patch by Aaron Gray.

llvm-svn: 93234
 2010-01-12 08:21:07 +00:00
David Greene
b879ff4855 Implement a feature (-vector-unaligned-mem) to allow targets to 
ignore alignment requirements for SIMD memory operands.  This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.

llvm-svn: 93151
 2010-01-11 16:29:42 +00:00
Evan Cheng
7cd6bfe549 Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size. 
llvm-svn: 91910
 2009-12-22 17:47:23 +00:00
Anton Korobeynikov
4e05e61a52 Bump alignment requirements for windows targets to achieve compartibility with vcpp. 
Based on patch by Michael Beck!

llvm-svn: 91745
 2009-12-19 02:04:23 +00:00
Evan Cheng
d97d025eba On recent Intel u-arch's, folding loads into some unary SSE instructions can 
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.

movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0

instead of
cvtss2sd (%rdi), %xmm0

An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0

llvm-svn: 91672
 2009-12-18 07:40:29 +00:00
Dan Gohman
3517f425b8 Target-independent support for TargetFlags on BlockAddress operands, 
and support for blockaddresses in x86-32 PIC mode.

llvm-svn: 89506
 2009-11-20 23:18:13 +00:00
David Goodwin
e1d06f2239 Allow target to specify regclass for which antideps will only be broken along the critical path. 
llvm-svn: 88682
 2009-11-13 19:52:48 +00:00
David Goodwin
93a4f29c67 Fixed to address code review. No functional changes. 
llvm-svn: 86634
 2009-11-10 00:48:55 +00:00
David Goodwin
538f9c25f8 Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies. 
llvm-svn: 86628
 2009-11-10 00:15:47 +00:00
Chris Lattner
25421b6954 indicate what the native integer types for the target are. 
Please verify.

llvm-svn: 86397
 2009-11-07 19:07:32 +00:00
Evan Cheng
0db11ae5a2 X86 needs critical path anti-dependency breaking. 
llvm-svn: 84931
 2009-10-23 05:57:35 +00:00
David Goodwin
82c1dd9754 Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none. 
llvm-svn: 84911
 2009-10-22 23:19:17 +00:00
Evan Cheng
eb82c3743a Turn on post-alloc scheduling for x86. 
llvm-svn: 84431
 2009-10-18 19:57:27 +00:00
Evan Cheng
1f32fa84b0 Oops. I forgot to change the tests first. Disable post-alloc scheduling. 
llvm-svn: 84425
 2009-10-18 18:31:31 +00:00
Evan Cheng
e921ebe70d -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed 
stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot 
move above a store of spill slot #2. 
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.

llvm-svn: 84424
 2009-10-18 18:16:27 +00:00
Evan Cheng
e1fbdc5244 Change createPostRAScheduler so it can be turned off at llc -O1. 
llvm-svn: 84273
 2009-10-16 21:06:15 +00:00
Evan Cheng
0a57c7d459 Remove X86Subtarget::IsLinux. It's no longer being used. 
llvm-svn: 84200
 2009-10-15 20:23:21 +00:00
Chris Lattner
e6bd7b39eb rearrange X86ATTAsmPrinter::doFinalization, making a scan of 
the global variable list only happen for COFF targets.

llvm-svn: 82010
 2009-09-16 05:20:33 +00:00
Daniel Dunbar
80f8fc8a2a Make these functions static and local. 
llvm-svn: 80892
 2009-09-03 05:47:34 +00:00
Evan Cheng
6d2d69faf9 X86JITInfo::getLazyResolverFunction() should not read cpu id to determine whether sse is available. Just use consult subtarget. 
No functionality changes.

llvm-svn: 80880
 2009-09-03 04:37:05 +00:00
Chris Lattner
c66a43e2b0 Add support for modeling whether or not the processor has support for 
conditional moves as a subtarget feature.  This is the easy part of 
PR4841.

llvm-svn: 80763
 2009-09-02 05:53:04 +00:00
Chris Lattner
c2a229453e change the -x86-asm-syntax=intel/att flag to be in X86TAI 
instead of X86 Subtarget.  This elimianates dependencies on
X86Subtarget from X86TAI.

llvm-svn: 78746
 2009-08-11 23:01:09 +00:00
Daniel Dunbar
0b82c938fe Normalize Subtarget constructors to take a target triple string instead of 
Module*.

Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.

llvm-svn: 77918
 2009-08-02 22:11:08 +00:00
Chris Lattner
478fc8442b remove the now-dead TM argument to these methods. 
llvm-svn: 75276
 2009-07-10 21:00:45 +00:00
Chris Lattner
9c13214ee8 make PIC vs DynamicNoPIC be explicit in PICStyles. 
llvm-svn: 75275
 2009-07-10 20:58:47 +00:00
Chris Lattner
9deef50410 add a couple of predicates to test for "stub style pic in PIC mode" and "stub style pic in dynamic-no-pic" mode. 
llvm-svn: 75273
 2009-07-10 20:47:30 +00:00
Chris Lattner
6097f82e18 simplify fast isel by using ClassifyGlobalReference. This 
elimiantes the last use of GVRequiresExtraLoad, so delete it.

llvm-svn: 75244
 2009-07-10 07:48:51 +00:00
Chris Lattner
7c038a2b3c eliminate GVRequiresRegister, replacing it with predicates we 
need for other purposes.

llvm-svn: 75243
 2009-07-10 07:38:24 +00:00