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Commit Graph

98946 Commits

Author SHA1 Message Date
Lang Hames
c4ef4936ff Add missing test case for r198737.
llvm-svn: 198772
2014-01-08 16:31:16 +00:00
Nico Rieck
38299d8a07 Remove mention of old deleted test scripts from testing guide
llvm-svn: 198771
2014-01-08 16:30:03 +00:00
Richard Sandiford
b971a7024a [DAGCombiner] Factor duplicated rotate code into a separate function
No functional change intended.

llvm-svn: 198768
2014-01-08 15:40:47 +00:00
Alp Toker
7638179115 lit: Provide file location in cfg error messages
Python doesn't do a good job at diagnosing string exec() so use execfile()
where available.

This should be a timesaver when trying to get to the bottom of build bot
failures.

Before:

    File "llvm/utils/lit/lit/TestingConfig.py", line 93, in load_from_path
      exec("exec data in cfg_globals")
    File "<string>", line 1, in <module>
    File "<string>", line 194, in <module>
  NameError: name 'typo' is not defined

After:

    File "llvm/utils/lit/lit/TestingConfig.py", line 95, in load_from_path
    execfile(path, cfg_globals)
    File "clang/test/lit.cfg", line 194, in <module>
      typo
      ^~~~
  NameError: name 'typo' is not defined

llvm-svn: 198766
2014-01-08 14:20:59 +00:00
David Woodhouse
444fbac42d [x86] Support R_386_PC8, R_386_PC16 and R_X86_64_PC8
llvm-svn: 198763
2014-01-08 12:58:40 +00:00
David Woodhouse
b662fe23a3 [x86] Add JMP_2 and other 16-bit PC-relative branch instructions
Mark them as requiring 16-bit mode for now, since we don't yet have
relaxation support for FK_Data_2.

llvm-svn: 198762
2014-01-08 12:58:36 +00:00
David Woodhouse
5c8e725a8c [x86] Do not relax PUSHi16 to PUSHi32 (PR18414)
They do *different* things to %esp, so they are not equivalent.

Rename PUSHi8 to PUSH32i8 and add the missing PUSH16i8.

llvm-svn: 198761
2014-01-08 12:58:32 +00:00
David Woodhouse
9dac8e32ee [x86] Make AsmParser validate registers for memory operands a bit better
We can't do a perfect job here. We *have* to allow (%dx) even in 64-bit
mode, for example, because it might be used for an unofficial form of
the in/out instructions. We actually want to do a better job of validation
*later*. Perhaps *instead* of doing it where we are at the moment.

But for now, doing what validation we *can* do in the place that the code
already has its validation, is an improvement.

llvm-svn: 198760
2014-01-08 12:58:28 +00:00
David Woodhouse
399c563e5e [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand
It seems there is no separate instruction class for having AdSize *and*
OpSize bits set, which is required in order to disambiguate between all
these instructions. So add that to the disassembler.

Hm, perhaps we do need an AdSize16 bit after all?

llvm-svn: 198759
2014-01-08 12:58:24 +00:00
David Woodhouse
b095fceafc [x86] Use 16-bit addressing where possible in 16-bit mode
Where "where possible" means that it's an immediate value and it's below
0x10000. In fact GAS will either truncate or error with larger values,
and will insist on using the addr32 prefix to get 32-bit addressing. So
perhaps we should do that, in a later patch.

llvm-svn: 198758
2014-01-08 12:58:18 +00:00
David Woodhouse
4e810363d9 [x86] Fix JCXZ,JECXZ_32 for 16-bit mode
JCXZ should have the 0x67 prefix only if we're in 32-bit mode, so make that
appropriately conditional. And JECXZ needs the prefix instead.

llvm-svn: 198757
2014-01-08 12:58:12 +00:00
David Woodhouse
e757b998ec [x86] Disambiguate RET[QL] and fix aliases for 16-bit mode
I couldn't see how to do this sanely without splitting RETQ from RETL.

Eric says: "sad about the inability to roundtrip them now, but...".
I have no idea what that means, but perhaps it wants preserving in the
commit comment.

llvm-svn: 198756
2014-01-08 12:58:07 +00:00
David Woodhouse
7d0744dadf [x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliases
llvm-svn: 198755
2014-01-08 12:57:55 +00:00
David Woodhouse
38e7bff9f3 [x86] Add JMP16[rm],CALL16[rm] instructions, and fix up aliases
llvm-svn: 198754
2014-01-08 12:57:49 +00:00
David Woodhouse
9c25ab3643 [x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit mode
llvm-svn: 198753
2014-01-08 12:57:45 +00:00
David Woodhouse
8bc826fd14 [x86] Add OpSize16 to instructions that need it
This fixes the bulk of 16-bit output, and the corresponding test case
x86-16.s now looks mostly like the x86-32.s test case that it was
originally based on. A few irrelevant instructions have been dropped,
and there are still some corner cases to be fixed in subsequent patches.

llvm-svn: 198752
2014-01-08 12:57:40 +00:00
Rafael Espindola
2bdcb192ba Use -std=gnu99 in tools/llvm-c-test/CMakeLists.txt
With a current mingw (gcc 4.8.1) it looks like we hit some variation of

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=40278

The end result is that off_t is not defined and the build fails without this
patch.

llvm-svn: 198749
2014-01-08 11:48:19 +00:00
Alp Toker
8a5e4a35de CMake: Provide LLVM_PLUGIN_EXT definition
This is needed to support the addition of tests for clang loadable plugins.

In clang, plugins are built as modules (bundles on OS X) rather than dynamic
libraries (dylib) so the build system needs to inform lit of the actual
file extension in use, typically '.so' on Unix and '.dll' on Windows.

(LLVM itself should probably switch to this scheme to fix PR14903 once and for
all.)

No change in build output or functionality intended.

llvm-svn: 198746
2014-01-08 11:10:24 +00:00
Elena Demikhovsky
1ecccf9364 AVX-512: Added more intrinsics for pmin/pmax, pabs, blend, pmuldq.
llvm-svn: 198745
2014-01-08 10:54:22 +00:00
Iain Sandoe
99b3d76928 [patch] Adjust behavior of FDE cross-section relocs for targets that don't support abs-differences.
Modern versions of OSX/Darwin's ld (ld64 > 97.17) have an optimisation present that allows the back end to omit relocations (and replace them with an absolute difference) for FDE some text section refs.

This patch allows a backend to opt-in to this behaviour by setting "DwarfFDESymbolsUseAbsDiff".  At present, this is only enabled for modern x86 OSX ports.

test changes by David Fang.

llvm-svn: 198744
2014-01-08 10:22:54 +00:00
Kevin Qin
fd4df4bd7a [AArch64 NEON] Fix generating incorrect value type of NEON_VDUPLANE
when lower build_vector if result value type mismatch with operand
value type.

llvm-svn: 198743
2014-01-08 08:06:14 +00:00
Venkatraman Govindaraju
0e7023f897 [SparcV9] Rename operands in some sparc64 instructions so that TableGen can encode them correctly.
llvm-svn: 198740
2014-01-08 07:47:57 +00:00
Venkatraman Govindaraju
31a117588f [Sparc] Correct the mask for fixup_sparc_br19.
llvm-svn: 198739
2014-01-08 06:46:51 +00:00
Venkatraman Govindaraju
d26e61b5c9 [Sparc] Add support for parsing branch instructions and conditional moves.
llvm-svn: 198738
2014-01-08 06:14:52 +00:00
Lang Hames
24d99bb391 Re-apply r196639: Add support for archives and object file caching under MCJIT.
I believe the bot failures on linux systems were due to overestimating the
alignment of object-files within archives, which are only guaranteed to be
two-byte aligned. I have reduced the alignment in
RuntimeDyldELF::createObjectImageFromFile accordingly.

llvm-svn: 198737
2014-01-08 04:09:09 +00:00
Saleem Abdulrasool
260d9a0786 tests: disable ARM unwinding tests if ARM is unavailable
Appease the buildbots for targets which do not build the ARM support by moving
the ARM specific test into a subdirectory and use the lit configuration to
disable them appropriately.

Thanks to chapuni and thakis for explaining how to do this!

llvm-svn: 198736
2014-01-08 03:44:01 +00:00
Saleem Abdulrasool
3374bbd05c ARM IAS: properly handle expression operands
Operands which involved label arithemetic would previously fail to parse.  This
corrects that by adding the additional case for the shift operand validation.

llvm-svn: 198735
2014-01-08 03:28:14 +00:00
Saleem Abdulrasool
869aa34c78 llvm-readobj: add support for ARM EHABI unwind info
This adds some preliminary support for decoding ARM EHABI unwinding information.
The major functionality that remains from complete support is bytecode
translation.

Each Unwind Index Table is printed out as a separate entity along with its
section index, name, offset, and entries.

Each entry lists the function address, and if possible, the name, of the
function to which it corresponds.  The encoding model, personality routine or
index, and byte code is also listed.

llvm-svn: 198734
2014-01-08 03:28:09 +00:00
Hao Liu
8c08e05c81 Fix a bug about generating undef operand when optimising shuffle vector and insert element in instruction combine.
llvm-svn: 198730
2014-01-08 03:06:15 +00:00
David Woodhouse
5bd74bdaf8 [x86] Kill gratuitous X86_{32,64}TargetMachine subclasses, use X86TargetMachine
llvm-svn: 198720
2014-01-08 00:08:50 +00:00
Rafael Espindola
4dc5af8bc2 Move the llvm mangler to lib/IR.
This makes it available to tools that don't link with target (like llvm-ar).

llvm-svn: 198708
2014-01-07 21:19:40 +00:00
Roman Divacky
5894163dfa In the ELFWriter when writing aliased (.set) symbols dont blindly
take type from the new symbol but merge them so that the type
is never "downgraded".

This is probably quite rare, except for IFUNC symbols which
we used to misassemble, losing the IFUNC type.

Fixes #18372.

llvm-svn: 198706
2014-01-07 20:17:03 +00:00
Cameron McInally
92630ae213 Fix uninitialized variable warning in DataLayout.
llvm-svn: 198702
2014-01-07 19:51:38 +00:00
Rafael Espindola
492c4c1202 Don't assert with private type info variables.
With the gnu objc runtime private strings are used. Since we only need to
produce a unique label, the fix is to just drop the asserts.

llvm-svn: 198701
2014-01-07 19:38:47 +00:00
Benjamin Kramer
07dd66b494 Emit arange padding with a single directive.
llvm-svn: 198700
2014-01-07 19:28:14 +00:00
David Peixotto
6a38357783 Add ARM fconsts/fconstd aliases for vmov.f32/vmov.f64
This commit adds the pre-UAL aliases of fconsts and fconstd for
vmov.f32 and vmov.f64. They use an InstAlias rather than a
MnemonicAlias to properly support the predicate operand.

We need to support encoded 8-bit constants in order to implement the
pre-UAL fconsts/fconstd aliases for vmov.f32/vmov.f64, so this
commit also fixes parsing of encoded floating point constants used
in vmov.f32/vmov.f64 instructions. Now we can support assembly code
like this:

  fconsts s0, #0x70

which is equivalent to vmov.f32 s0, #1.0.

Most of the code was already in place to support this feature.
Previously the code was trying to accept encoded 8-bit float
constants for the vmov.f32/vmov.f64 instructions.  It looks like the
support for parsing encoded floats was lost in a refactoring in
commit r148556 and we did not have any tests in place to catch it.

The change in this commit is to keep the parsed value as a 32-bit
float instead of a 64-bit double because that is what the isFPImm()
function expects to find. There is no loss of precision by using a
32-bit float here because we are still limited to an 8-bit encoded
value in the end.

Additionally, we explicitly reject encoded 8-bit floats for
vmovf.32/64. This is the same as the current behavior, but we now do
it explicitly rather than accidently.

llvm-svn: 198697
2014-01-07 18:19:23 +00:00
Logan Chien
4508cd2773 [arm] Fix an incorrect comment in ARMUnwindOpAsm.h.
llvm-svn: 198696
2014-01-07 17:47:25 +00:00
Chandler Carruth
c991958746 Try to fix the windows build. The comments in other files don't seem to
be quite accurate. =]

llvm-svn: 198690
2014-01-07 12:37:13 +00:00
Chandler Carruth
7aa902a488 Move the LLVM IR asm writer header files into the IR directory, as they
are part of the core IR library in order to support dumping and other
basic functionality.

Rename the 'Assembly' include directory to 'AsmParser' to match the
library name and the only functionality left their -- printing has been
in the core IR library for quite some time.

Update all of the #includes to match.

All of this started because I wanted to have the layering in good shape
before I started adding support for printing LLVM IR using the new pass
infrastructure, and commandline support for the new pass infrastructure.

llvm-svn: 198688
2014-01-07 12:34:26 +00:00
Chandler Carruth
87f14b4eec Re-sort all of the includes with ./utils/sort_includes.py so that
subsequent changes are easier to review. About to fix some layering
issues, and wanted to separate out the necessary churn.

Also comment and sink the include of "Windows.h" in three .inc files to
match the usage in Memory.inc.

llvm-svn: 198685
2014-01-07 11:48:04 +00:00
Hao Liu
2324cab69b [AArch64]Add support to spill/fill D tuples such as DPair/DTriple/DQuad. There is no test cases for D tuple as the original test cases are too large. As the spill/fill of the D tuple is similar to the Q tuple, the correctness can be guaranteed.
llvm-svn: 198684
2014-01-07 10:50:43 +00:00
NAKAMURA Takumi
ed96e58eb4 [CMake] Introduce llvm_update_compile_flags(target_name) to update compile flags in target properties.
FIXME: Just add_unittest() is using it.
FIXME: Cooperate with source properties.
llvm-svn: 198683
2014-01-07 10:24:14 +00:00
Hao Liu
bbb265cfee [AArch64]Add support to copy D tuples such as DPair/DTriple/DQuad and Q tuples such as QPair/QTriple/QQuad. There is no test case for D tuple as the original test cases are too large. As the copy of the D tuple is similar to the Q tuple, the correctness can be guaranteed.
llvm-svn: 198682
2014-01-07 10:00:03 +00:00
Venkatraman Govindaraju
69760d5a12 [Sparc] Add support for parsing sparc asm modifiers such as %hi, %lo etc.,
Also, correct the offsets for FixupsKindInfo.

llvm-svn: 198681
2014-01-07 08:00:49 +00:00
Andrew Trick
d008071ce2 Fix for PR18396: Assertion: MO->isDead "Cannot fold physreg def".
InlineSpiller::foldMemoryOperand needs to handle undef call operands.

llvm-svn: 198679
2014-01-07 07:31:10 +00:00
Andrew Trick
bb6ce38639 Reapply r198654 "indvars: sink truncates outside the loop."
This doesn't seem to have actually broken anything. It was paranoia
on my part. Trying again now that bots are more stable.

This is a follow up of the r198338 commit that added truncates for
lcssa phi nodes. Sinking the truncates below the phis cleans up the
loop and simplifies subsequent analysis within the indvars pass.

llvm-svn: 198678
2014-01-07 06:59:12 +00:00
Kevin Qin
cb6af368ab [AArch64 NEON] Fixed incorrect immediate used in BIC instruction.
llvm-svn: 198675
2014-01-07 05:10:47 +00:00
Saleem Abdulrasool
90329d7060 ARM IAS: allow more depth in contextual diagnostics
Switch the context to be SmallVectors.  This allows for saving additional
context when providing previous emission sites.

llvm-svn: 198665
2014-01-07 02:29:00 +00:00
Saleem Abdulrasool
58df683088 ARM IAS: refactor unwind context
Move the unwinding context for the ARM IAS into a helper class.  This is purely
a structural refactoring.  A follow up change allows for recording additional
depth to improve diagnostics.

llvm-svn: 198664
2014-01-07 02:28:55 +00:00
Saleem Abdulrasool
ce9f4e943f ARM Streamer: print out tag names
If using verbose asm, print out the friendly name of the tag if possible.

llvm-svn: 198663
2014-01-07 02:28:50 +00:00