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Commit Graph

104858 Commits

Author SHA1 Message Date
Rafael Espindola
526c55c690 Remove unused and odd code.
This code was never being used and any use of it would look fairly strange.
For example, it would try to map a object_error::parse_failed to
std::errc::invalid_argument.

llvm-svn: 210912
2014-06-13 15:36:17 +00:00
Rafael Espindola
7e55e0d1f5 Remove broken include.
Looks like I got some git merge wrong.

llvm-svn: 210911
2014-06-13 15:21:50 +00:00
Rafael Espindola
4e05d93641 Fix KillTheDoctor after r210725.
We don't map these windows errors to generic ones since errc::timed_out is
not defined on mingw. Just use the raw windows error value.

llvm-svn: 210910
2014-06-13 15:01:11 +00:00
Tim Northover
d7c66da372 SCCP: update for cmpxchg returning { iN, i1 } now.
I accidentally missed this one since its use looked OK locally.

llvm-svn: 210909
2014-06-13 14:54:09 +00:00
Zoran Jovanovic
4cfd6b9828 [mips][mips64r6] Relocation R_MIPS_PC18_S3
Differential Revision: http://reviews.llvm.org/D3890

llvm-svn: 210908
2014-06-13 14:26:47 +00:00
Tim Northover
60239709b1 Docs: remove extra {} around result types.
It makes the types look like they're single-element structures. And
when we have instructions that *do* result in a struct, that can get
confusing rather quickly.

llvm-svn: 210905
2014-06-13 14:24:23 +00:00
Tim Northover
e69e6a34bf Docs: fix grammar error in description
llvm-svn: 210904
2014-06-13 14:24:16 +00:00
Tim Northover
b9ec29d7c5 IR: add "cmpxchg weak" variant to support permitted failure.
This commit adds a weak variant of the cmpxchg operation, as described
in C++11. A cmpxchg instruction with this modifier is permitted to
fail to store, even if the comparison indicated it should.

As a result, cmpxchg instructions must return a flag indicating
success in addition to their original iN value loaded. Thus, for
uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The
second flag is 1 when the store succeeded.

At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been
added as the natural representation for the new cmpxchg instructions.
It is a strong cmpxchg.

By default this gets Expanded to the existing ATOMIC_CMP_SWAP during
Legalization, so existing backends should see no change in behaviour.
If they wish to deal with the enhanced node instead, they can call
setOperationAction on it. Beware: as a node with 2 results, it cannot
be selected from TableGen.

Currently, no use is made of the extra information provided in this
patch. Test updates are almost entirely adapting the input IR to the
new scheme.

Summary for out of tree users:
------------------------------

+ Legacy Bitcode files are upgraded during read.
+ Legacy assembly IR files will be invalid.
+ Front-ends must adapt to different type for "cmpxchg".
+ Backends should be unaffected by default.

llvm-svn: 210903
2014-06-13 14:24:07 +00:00
Cameron McInally
c8c6e33610 Fix bad copy-and-paste from r210652. AVX512 masked leading zero intrinsics.
llvm-svn: 210901
2014-06-13 13:20:01 +00:00
Daniel Sanders
fe8b495815 [mips] Add cache and pref instructions
Summary:
cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in
MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset
available to earlier cores.

Resolved the decoding conflict between pref and lwc3.

Depends on D4115

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4116

llvm-svn: 210900
2014-06-13 13:15:59 +00:00
Daniel Sanders
6b0e7f80e4 [mips][mips64r6] bc1any[24] are not available on MIPS32r6/MIPS64r6
Summary:
These MIPS-3D instructions have never been implemented in LLVM so we only
add testcases.

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4115

llvm-svn: 210899
2014-06-13 13:08:38 +00:00
Daniel Sanders
bd7f506062 [mips][mips64r6] b(ge|lt)zal are not available on MIPS32r6/MIPS64r6 and bal is a normal instruction
Summary:
b(ge|lt)zal have been removed in MIPS32r6/MIPS64r6. However, bal (an alias
for 'bgezal $zero, $offset') still remains with the same encoding it had
prior to MIPS32r6/MIPS64r6.

Updated the MipsNaCLELFStreamer, and MipsLongBranch to correctly handle the
MIPS32r6/MIPS64r6 BAL instruction in addition to the existing BAL_BR pseudo.

No changes were required to the CodeGen test that looks for BAL
(test/CodeGen/Mips/longbranch.ll) since the new instruction has the same
syntax.

Depends on D4113

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4114

llvm-svn: 210898
2014-06-13 13:02:52 +00:00
Daniel Sanders
364b414f44 [mips][mips64r6] daddi is not available on MIPS64r6
Summary:
It's not emitted by the code generator so we only need assembler tests.

Also added missing daddi aliases from dsub mnemonics, and removed a couple
duplicate dsub tests.

Depends on D4112

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4113

llvm-svn: 210897
2014-06-13 12:49:06 +00:00
NAKAMURA Takumi
4355be35c6 [Win32] Let utils/not aware of abort(), aka llvm_unreachable(), in msvcrt.
It has exit code as 3. abort(), aka unreachable, may be handled as crash.

FIXME: Could we move this into Win32/Program.inc?
llvm-svn: 210895
2014-06-13 12:23:56 +00:00
NAKAMURA Takumi
55149aa040 llvm/test/CodeGen/X86/fast-isel-args-fail2.ll: Don't expect to fail with -Asserts. It might or might not crash.
llvm-svn: 210894
2014-06-13 12:05:06 +00:00
Cameron McInally
8909338d50 Add HasCDI predicate to AVX512 VPBROADCASTM*.
llvm-svn: 210892
2014-06-13 11:40:31 +00:00
Tim Northover
4a6737b5fc CPP backend: set volatile property on atomic instructions.
llvm-svn: 210890
2014-06-13 09:14:50 +00:00
Oliver Stannard
e34249bacf ARM: Fix fastcc calling convention for Thumb1
When targetting Thumb1 on a processor which has a VFP unit (which
is not accessible from Thumb1), we were converting the fastcc calling
convention to AAPCS-VFP, which is not possible.

llvm-svn: 210889
2014-06-13 08:33:03 +00:00
Matt Arsenault
dce27c2477 R600: Don't call setOperationAction with things that aren't opcodes.
CondCode actions are set with setCondCodeAction.
This should have been a harmless bug since the values seem to only
collide only with nodes that don't need to be handled, and these are
already correctly setup elsewhere.

llvm-svn: 210888
2014-06-13 07:44:38 +00:00
Matt Arsenault
e8c6185eba R600/SI: Fix selection error on i64 rotl / rotr.
Evergreen is still broken due to missing shl_parts.

llvm-svn: 210885
2014-06-13 04:00:30 +00:00
Rafael Espindola
ce20ee3e79 Remove the last uses of 'using std::error_code'
This finishes the transition to std::error_code.

llvm-svn: 210877
2014-06-13 03:20:08 +00:00
Rafael Espindola
5c15b3d369 Remove 'using std::error_code' from tools.
llvm-svn: 210876
2014-06-13 03:07:50 +00:00
Rafael Espindola
251ce700f0 Fix build on windows.
llvm-svn: 210873
2014-06-13 02:36:09 +00:00
Rafael Espindola
98710599c1 Remove 'using std::errro_code' from lib.
llvm-svn: 210871
2014-06-13 02:24:39 +00:00
Juergen Ributzka
9f0822c470 [FastISel][X86] Add support for cvttss2si/cvttsd2si intrinsics.
This adds support for the cvttss2si/cvttsd2si intrinsics. Preceding
insertelement instructions are folded into the conversion instruction (if
possible).

llvm-svn: 210870
2014-06-13 02:21:58 +00:00
Tom Stellard
b563645bdf R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtarget
llvm-svn: 210869
2014-06-13 01:32:00 +00:00
Tom Stellard
3e20fabeaf R600: Drop use of cached TargetMachine in R600InstrInfo.cpp
llvm-svn: 210868
2014-06-13 01:31:56 +00:00
Rafael Espindola
e726a14d05 Remove all uses of 'using std::error_code' from headers.
llvm-svn: 210866
2014-06-13 01:25:41 +00:00
Tom Stellard
2da22cc495 R600: Drop use of cached TargetMachine in AMDGPUInstrInfo.cpp
llvm-svn: 210865
2014-06-13 01:02:57 +00:00
Juergen Ributzka
be48c6b01a [FastISel][X86] - Add branch weights
Add branch weights to branch instructions, so that the following passes can
optimize based on it (i.e. basic block ordering).

llvm-svn: 210863
2014-06-13 00:45:11 +00:00
Eric Christopher
825e0c609b Move ARMSelectionDAGInfo from the TargetMachine to the subtarget.
llvm-svn: 210862
2014-06-13 00:20:39 +00:00
Eric Christopher
19f9acc9ab Move to a private function to initialize subtarget dependencies
so we can use initializer lists for the ARMSubtarget and then
use this to initialize a moved DataLayout on the subtarget from
the TargetMachine.

llvm-svn: 210861
2014-06-13 00:20:35 +00:00
Alexey Samsonov
11cb912a27 [DWARF parser] Fix broken address ranges construction.
Previous algorithm for constructing [Address ranges]->[Compile Units]
mapping was wrong. It somewhat relied on the assumption that address ranges
for different compile units may not overlap. It is not so.
For example, two compile units may contain the definition of the same
linkonce_odr function. These definitions will be merged at link-time,
resulting in equivalent .debug_ranges entries for both these units

Instead of sorting and merging original address ranges (from .debug_ranges
and .debug_aranges), implement a different approach: save endpoints
of all ranges, and then use a sweep-line approach to construct
the desired mapping. If we find that certain address maps to
several compilation units, we just pick any of them.

llvm-svn: 210860
2014-06-12 23:58:49 +00:00
Eric Christopher
234efcaac4 Have ARMSelectionDAGInfo take a DataLayout as it's argument as the
DAG has access to the subtarget and TargetSelectionDAGInfo only
needs a DataLayout.

llvm-svn: 210859
2014-06-12 23:39:49 +00:00
Juergen Ributzka
9dda2c5782 [FastISel][X86] Add MachineMemOperand to load/store instructions.
This commit adds MachineMemOperands to load and store instructions. This allows
the peephole optimizer to fold load instructions. Unfortunatelly the peephole
optimizer currently doesn't run at -O0.

llvm-svn: 210858
2014-06-12 23:27:57 +00:00
Eric Christopher
286dd39af0 Move the PPCSelectionDAGInfo off the TargetMachine and onto the
subtarget.

llvm-svn: 210854
2014-06-12 23:02:32 +00:00
Eric Christopher
0382d62f87 Make PPCSelectionDAGInfo take a DataLayout instead of a TargetMachine
since that's all it needs.

llvm-svn: 210853
2014-06-12 22:56:48 +00:00
Eric Christopher
42e57db35c Move PPCTargetLowering off of the TargetMachine and onto the subtarget.
llvm-svn: 210852
2014-06-12 22:50:10 +00:00
Eric Christopher
576f8a1a6b Remove an extraneous this-> to access the subtarget.
llvm-svn: 210849
2014-06-12 22:38:20 +00:00
Eric Christopher
d1b1190bd1 Rename PPCSubTarget to Subtarget in PPCTargetLowering for consistency.
Also remove an extra local subtarget in the initialization functions.

llvm-svn: 210848
2014-06-12 22:38:18 +00:00
Andrew Trick
e967f1bca1 Fix the scheduler's MaxObservedStall computation.
WenHan Gu pointed out this bug that results in an assert
not being effective in some cases.

llvm-svn: 210846
2014-06-12 22:36:28 +00:00
Eric Christopher
429be5d609 Move PPCJITInfo off of the TargetMachine and onto the subtarget.
Needed to migrate a few functions around to avoid circular header
dependencies.

llvm-svn: 210845
2014-06-12 22:28:06 +00:00
Eric Christopher
40ba57e7f5 Remove the use of TargetMachine from PPCJITInfo and replace with
the subtarget. Also remove unnecessary argument to the constructor
at the same time, we already have access via the subtarget.

llvm-svn: 210844
2014-06-12 22:19:51 +00:00
Rafael Espindola
b71c530515 Fix the build of KillTheDoctor.
llvm-svn: 210843
2014-06-12 22:16:55 +00:00
Richard Smith
33366241df [modules] The LLVM C API does not require C++!
llvm-svn: 210842
2014-06-12 22:09:39 +00:00
Eric Christopher
95b7901fd6 Move PPCInstrInfo off of the target machine and onto the subtarget.
llvm-svn: 210839
2014-06-12 22:05:46 +00:00
Rafael Espindola
a507565994 Try to fix the windows build.
llvm-svn: 210837
2014-06-12 21:53:57 +00:00
Eric Christopher
d4532ed073 Remove TargetMachine from PPCInstrInfo and all dependencies and
replace with the current subtarget.

llvm-svn: 210836
2014-06-12 21:48:52 +00:00
Rafael Espindola
e0e308ff6d Don't use 'using std::error_code' in include/llvm.
This should make sure that most new uses use the std prefix.

llvm-svn: 210835
2014-06-12 21:46:39 +00:00
Bob Wilson
1028f7685a Move test for r210734 to Feature/aliases.ll.
llvm-svn: 210833
2014-06-12 21:37:30 +00:00