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Author SHA1 Message Date
Chad Rosier
73d8191b27 Whitespace. 
llvm-svn: 153105
 2012-03-20 18:38:33 +00:00
Chad Rosier
ffd2dbd676 [avx] Move the vextractf128 patterns closer to the vextractf128 def. Remove 
whitespace from test case.  No functional change intended.

llvm-svn: 153103
 2012-03-20 18:24:55 +00:00
Kevin Enderby
b87e1e0bfd Fix assembling ARM vst2 instructions with double-spaced registers. 
llvm-svn: 153099
 2012-03-20 17:41:51 +00:00
Jim Grosbach
b562c4f2fa ARM non-scattered MachO relocations for movw/movt. 
Needed when building -mdynamic-no-pic code.

rdar://10459256

llvm-svn: 153097
 2012-03-20 17:25:45 +00:00
Chad Rosier
c667f10cbb Fix test. 
llvm-svn: 153095
 2012-03-20 17:20:46 +00:00
Chad Rosier
143f33dc92 [avx] Adjust the VINSERTF128rm pattern to allow for unaligned loads. 
This results in things such as

	vmovups	16(%rdi), %xmm0
	vinsertf128	$1, %xmm0, %ymm0, %ymm0

to be combined to

    vinsertf128	$1, 16(%rdi), %ymm0, %ymm0

rdar://11076953

llvm-svn: 153092
 2012-03-20 17:08:51 +00:00
Silviu Baranga
d20ed770e5 The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. 
llvm-svn: 153089
 2012-03-20 15:54:56 +00:00
Silviu Baranga
e5abcac828 test commit 
llvm-svn: 153086
 2012-03-20 13:12:38 +00:00
Richard Barton
25f44c807b Test Commit - add a newline 
llvm-svn: 153083
 2012-03-20 10:50:35 +00:00
Bill Wendling
338ddac8f7 It's possible to have a constant expression who's size is quite big (e.g., 
i128). In that case, we may not be able to print out the MCExpr as an
expression. For instance, we could have an MCExpr like this:

    0xBEEF0000BEEF0000 | (0xBEEF0000BEEF0000 << 64)

The MCExpr printer handles sizes up to 64-bits, but this expression would
require 128-bits. In this situation, try to evaluate the constant expression and
emit that as the value into 64-bit chunks.
<rdar://problem/11070338>

llvm-svn: 153081
 2012-03-20 08:56:43 +00:00
Craig Topper
61aa773498 Remove code that prevented lowering shuffles if they are used by load and themselves used by a extract_vector_elt. This was done to allow the DAG combiner to collapse to a single element load. Unfortunately, sometimes the extract_vector_elt would disappear before DAG combine could do the transformation leaving a vector_shuffle that isel couldn't handle. New code lets the shuffle be converted to a target specific node, but then adds a combine routine that can convert target specific nodes back to vector_shuffles if the folding criteria are met. 
llvm-svn: 153080
 2012-03-20 07:17:59 +00:00
Craig Topper
de938c64eb Factor out target shuffle mask decoding from getShuffleScalarElt and use a SmallVector of int instead of unsigned for shuffle mask in decode functions. Preparation for another change. 
llvm-svn: 153079
 2012-03-20 06:42:26 +00:00
Craig Topper
6bea69c868 When combining (vextract shuffle (load ), <1,u,u,u>), 0) -> (load ), add users of the final load to the worklist too. Needed by changes I'm preparing to make to X86 backend. 
llvm-svn: 153078
 2012-03-20 05:28:39 +00:00
Eric Christopher
fea2d0f83a Do everything up to generating code to try to get a register for 
a variable. The previous code would break the debug info changing
code invariant. This will regress debug info for arguments where
we elide the alloca created.

Fixes rdar://11066468

llvm-svn: 153074
 2012-03-20 01:07:58 +00:00
Eric Christopher
0a61365e70 Untabify. 
llvm-svn: 153073
 2012-03-20 01:07:56 +00:00
Eric Christopher
9907ef1870 Add another debugging statement here. 
llvm-svn: 153072
 2012-03-20 01:07:53 +00:00
Eric Christopher
1829ce5f46 Use lookUpRegForValue here instead of duplicating the code. 
llvm-svn: 153071
 2012-03-20 01:07:47 +00:00
Chris Lattner
e3575252ce Fix two bugpoint bugs: 
1) opt is not usually in the same path as the target program. Even for
the bugpoint as a standalone app, it should be more portable to search
in PATH, isn't it?
2) bugpoint driver accounts opt plugins, but does not list them in the
final output command.

Patch by Dmitry Mikushin!

llvm-svn: 153066
 2012-03-19 23:42:11 +00:00
Chris Lattner
688f466fd4 fix PR12301 - llvm-bcanalyze should print to stdout, not stderr (except for errors). 
llvm-svn: 153065
 2012-03-19 23:40:48 +00:00
Pete Cooper
fe0c08a32a f16 FDIV can now be legalized by promoting to f32 
llvm-svn: 153064
 2012-03-19 23:38:12 +00:00
Chris Lattner
9d0338734a fix a build failure with libc++ 
llvm-svn: 153063
 2012-03-19 23:31:01 +00:00
Jim Grosbach
0ca6b4a15d ARM branch relaxation for unconditional t1 branches. 
rdar://11059157

llvm-svn: 153055
 2012-03-19 21:32:32 +00:00
Jim Grosbach
65c7d4dab9 ARM assembly, accept optional '#' on lane index number. 
rdar://11057160

llvm-svn: 153053
 2012-03-19 20:39:53 +00:00
Michael J. Spencer
e5d5ca4072 [Object/COFF]: Expose getSectionContents. 
llvm-svn: 153051
 2012-03-19 20:27:37 +00:00
Michael J. Spencer
2174510edf [Object/COFF]: Expose getSectionName. 
Also add some documentation.

llvm-svn: 153050
 2012-03-19 20:27:15 +00:00
Anton Korobeynikov
ccc669ff8f Perform mul combine when multiplying wiht negative constants. 
Patch by Weiming Zhao!
This fixes PR12212

llvm-svn: 153049
 2012-03-19 19:19:50 +00:00
Lang Hames
e9e9965da5 Add an option to the MI scheduler to cut off scheduling after a fixed number of 
instructions have been scheduled. Handy for tracking down scheduler bugs, or
bugs exposed by scheduling.

llvm-svn: 153045
 2012-03-19 18:38:38 +00:00
Kostya Serebryany
f8cb0a65c1 [asan] don't emit __asan_mapping_offset/__asan_mapping_scale by default -- they are currently used only for experiments 
llvm-svn: 153040
 2012-03-19 16:40:35 +00:00
NAKAMURA Takumi
41690b3b7f llvm/test/DebugInfo: Move two tests to DebugInfo/X86. They are X86-dependent. 
llvm-svn: 153038
 2012-03-19 16:16:03 +00:00
Duncan Sands
725ed6d921 Fix DAG combine which creates illegal vector shuffles. Patch by Heikki Kultala. 
llvm-svn: 153035
 2012-03-19 15:35:44 +00:00
Preston Gurd
d1ae391210 This patch adds X86 instruction itineraries for non-pseudo opcodes in 
X86InstrCompiler.td.
 
It also adds –mcpu-generic to the legalize-shift-64.ll test so the test
will pass if run on an Intel Atom CPU, which would otherwise
produce an instruction schedule which differs from that which the test expects.

llvm-svn: 153033
 2012-03-19 14:10:12 +00:00
Benjamin Kramer
080ccc13a6 Add a note for -ffast-math optimization of vector norm. 
llvm-svn: 153031
 2012-03-19 00:43:34 +00:00
Chandler Carruth
f79b13d9c4 Make the formatting of this file more consistent, and fix the 80-columns 
violations I introduced. Also sort some of the instructions to get
a more consistent ordering.

Suggestions on still better / more consistent formatting would be
welcome. I'm actually tempted to use a macro to define all of the
delegate methods...

llvm-svn: 153030
 2012-03-18 23:45:14 +00:00
Chandler Carruth
6163cc0a2f Teach InstVisitor about the UnaryInstruction layer in the instruction 
type hierarchy. I wanted to use this for the inline cost rewrite, and
found it was missing.

llvm-svn: 153029
 2012-03-18 23:31:28 +00:00
Nick Lewycky
92a7d87ceb Factor out the multiply analysis code in ComputeMaskedBits and apply it to the 
overflow checking multiply intrinsic as well.

Add a test for this, updating the test from grep to FileCheck.

llvm-svn: 153028
 2012-03-18 23:28:48 +00:00
Craig Topper
34891f519c isCommutedMOVLMask should only look at 128-bit vectors to match isMOVLMask. 
llvm-svn: 153027
 2012-03-18 22:50:10 +00:00
Nick Lewycky
bc6d9e5b06 This clause (although matching parts of the implementation) can't be correct. 
Thanks to Eli for noticing the discrepancy.

llvm-svn: 153011
 2012-03-18 09:35:50 +00:00
Benjamin Kramer
5cfc07cf35 CriticalAntiDepBreaker: Replace a SmallSet of regs with a much denser BitVector. 
llvm-svn: 152999
 2012-03-17 20:22:57 +00:00
Craig Topper
b1f171a213 Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 
llvm-svn: 152997
 2012-03-17 18:46:09 +00:00
Benjamin Kramer
ad7378e585 MachineInstr: Inline the fast path (non-bundle instruction) of hasProperty. 
This is particularly helpful as both arguments tend to be constants.

llvm-svn: 152991
 2012-03-17 17:03:45 +00:00
Craig Topper
bb72c24507 Fix some copy and paste remnants of Cell and SPU in Hexagon files. 
llvm-svn: 152981
 2012-03-17 09:39:20 +00:00
Craig Topper
41786f284d Fix typo in file header. 
llvm-svn: 152980
 2012-03-17 09:28:37 +00:00
Craig Topper
3d39a3e5ba Pass TargetOptions to HexagonTargetMachine constructor by reference to match other targets and the base class. 
llvm-svn: 152979
 2012-03-17 09:24:09 +00:00
Craig Topper
0534d071b7 Reorder includes to match coding standards. Fix an issue or two exposed by that. 
llvm-svn: 152978
 2012-03-17 07:33:42 +00:00
Jim Grosbach
138c2143c3 MC asm parser macro argument count was wrong when empty. 
evaluated to '1' when the argument list was empty (should be '0').

rdar://11057257

llvm-svn: 152967
 2012-03-17 00:11:42 +00:00
Bill Wendling
b427a9f177 Check if we can handle the arguments of a call (and therefore the call) in 
fast-isel before emitting code. If the program bails after code was emitted,
then it could lead to the stack being adjusted more than once (two
CALLSEQ_BEGINs emitted) but being adjuste back only once after the call. This
leads to general badness and gnashing of teeth.
<rdar://problem/11050630>

llvm-svn: 152959
 2012-03-16 23:11:07 +00:00
Francois Pichet
d7e89c29c2 Revert r152915. Chapuni's WinWaitReleased refactoring: It doesn't work for me 
llvm-svn: 152958
 2012-03-16 22:50:01 +00:00
Chris Lattner
b39bdf2c78 clarify the coding standards a bit. 
llvm-svn: 152957
 2012-03-16 22:34:37 +00:00
Jim Grosbach
7ab12a079f ARM fix silly typo in optional operand alias. 
rdar://11065671

llvm-svn: 152954
 2012-03-16 22:18:29 +00:00
Jim Grosbach
99aef428f3 ARM divided syntax fmrx/fmxr mnemonics. 
llvm-svn: 152946
 2012-03-16 21:06:13 +00:00