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Commit Graph

198000 Commits

Author SHA1 Message Date
Guillaume Chatelet
c5c79e3df8 [Alignment][NFC] Migrate CallingConv tablegen code
Summary: This is a follow up on D81196, fixing one more call site.

Reviewers: courbet

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81268
2020-06-08 06:58:02 +00:00
Max Kazantsev
ad2f7fe780 [Test] Add test showing InstCombine missing simplification opportunity 2020-06-08 13:19:09 +07:00
Craig Topper
54deaf9887 [X86] Support load shrinking for strict fp nodes in combineCVTPH2PS 2020-06-07 21:09:55 -07:00
QingShan Zhang
0b625d79a2 [NFC] Remove the extra ; to avoid the warning of build compiler 2020-06-08 03:51:05 +00:00
Nemanja Ivanovic
755e1e67f9 [PowerPC] Do not assume operand of ADDI is an immediate
After pseudo-expansion, we may end up with ADDI (add immediate)
instructions where the operand is not an immediate but a relocation.
For such instructions, attempts to get the immediate result in
assertion failures for obvious reasons.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=45432
2020-06-07 22:18:31 -05:00
Craig Topper
c3746fcd71 [X86] Improve (vzmovl (insert_subvector)) combine to handle a bitcast between the vzmovl and insert
This combine tries shrink a vzmovl if its input is an
insert_subvector. This patch improves it to turn
(vzmovl (bitcast (insert_subvector))) into
(insert_subvector (vzmovl (bitcast))) potentially allowing the
bitcast to be folded with a load.
2020-06-07 19:31:06 -07:00
Craig Topper
6d167c498f [X86] Teach combineCVTP2I_CVTTP2I to handle STRICT_CVTTP2SI/STRICT_CVTTP2UI
Allows us to shrink 128-bit simple load to enable folding for
v2f32->v2i64 vcvttps2qq/vcvttps2uqq.
2020-06-07 19:31:06 -07:00
QingShan Zhang
a619e90821 [Power9] Add addi post-ra scheduling heuristic
The instruction addi is usually used to post increase the loop indvar, which looks like this:

label_X:
 load x, base(i)
 ...
 y = op x
 ...
 i = addi i, 1
 goto label_X

However, for PowerPC, if there are too many vsx instructions that between y = op x and  i = addi i, 1,
it will use all the hw resource that block the execution of i = addi, i, 1, which result in the stall
of the load instruction in next iteration. So, a heuristic is added to move the addi as early as possible
to have the load hide the latency of vsx instructions, if other heuristic didn't apply to avoid the starve.

Reviewed By: jji

Differential Revision: https://reviews.llvm.org/D80269
2020-06-08 01:31:07 +00:00
Craig Topper
10c2d5387d [X86] Don't scalarize v2f32->v2i64 strict_fp_to_sint/uint with avx512dq and not avx512vl.
We can pad the v2f32 with 0s up to v8f32 and use a v8f32->v8i64
operation. This is what we end up with on non-strict nodes except
we don't pad with 0s since we don't care about exceptions.
2020-06-07 14:45:26 -07:00
Benjamin Kramer
ce9aba2e75 SmallPtrSet::find -> SmallPtrSet::count
The latter is more readable and more efficient. While there clean up
some double lookups. NFCI.
2020-06-07 22:38:08 +02:00
Simon Pilgrim
73d41f52ec [X86][AVX2] combineSetCCMOVMSK - handle all_of patterns for PMOVMSKB(PACKSSBW(LO(X), HI(X)))
In the sign splat case, we can fold PMOVMSKB(PACKSSBW(LO(X), HI(X))) -> PMOVMSKB(BITCAST_v32i8(X)) without introducing a signmask + comparison (which unlike for any_of won't fold into a single TEST).
2020-06-07 21:08:53 +01:00
Fangrui Song
8f386754d9 [gcov] Support .gcno/.gcda in gcov 8, 9 or 10 compatible formats 2020-06-07 11:27:49 -07:00
AK
60d72160a7 Add cl::ZeroOrMore to get around build system issues
It is quite common to get multiple instances of optimization flags while building.
The following optimizations does not have cl::ZeroOrMore which causes errors during the build.

Reviewers: alexbdv,spop

Differential Revision: https://reviews.llvm.org/D81187
2020-06-07 10:15:18 -07:00
Kang Zhang
9e16b5cc8b [NFC][PowerPC] Add a new case to test ctrloop for fp128 2020-06-07 16:35:32 +00:00
Simon Pilgrim
fd063e3d81 CFG.h - reduce includes to forward declarations. NFC. 2020-06-07 17:25:35 +01:00
Benjamin Kramer
2edefd0250 Unbreak the build 2020-06-07 18:17:21 +02:00
Simon Pilgrim
b17630c898 DomTreeUpdater.h - refine includes. NFC.
We don't need any of its defs or many of its includes inside PostDominators.h - so split it and reduce the frontend load.
2020-06-07 16:57:48 +01:00
Shawn Landden
89f3e32383 [AArch64] add test for large popcount; NFC 2020-06-07 19:20:33 +04:00
Sanjay Patel
f8f4aec997 [Docs] fix typos for llvm-mca; NFC 2020-06-07 11:14:24 -04:00
Simon Pilgrim
914dcfee22 [X86][SSE] combineSetCCMOVMSK - add initial support for allof patterns.
Handle MOVMSK 'allof' comparisons (X86ISD::SUB X, AllBitsMask) as well as 'anyof' patterns.

This allows us to handle these patterns in the MOVMSK(BITCAST(X)) pattern to fix PR37087.
2020-06-07 16:10:13 +01:00
Fangrui Song
d6e9f4ed95 [llvm-cov] Fix gcov version detection on big-endian 2020-06-07 08:07:32 -07:00
Xing GUO
69a07af4a7 [ObjectYAML][test] Address comments in D80203
This patch addresses comments in [D80203](https://reviews.llvm.org/D80203?vs=on&id=266415&whitespace=ignore-most#2062287)

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D80862
2020-06-07 22:55:33 +08:00
Xing GUO
0c632b355b [DWARFYAML][debug_ranges] Fix inappropriate assertion. NFC. 2020-06-07 22:45:52 +08:00
Sanjay Patel
590515a326 [InstCombine] fold mask op into casted shift (PR46013)
https://rise4fun.com/Alive/Qply8

  Pre: C2 == (-1 u>> zext(C1))
  %a = ashr %x, C1
  %s = sext %a to i16
  %r = and i16 %s, C2
    =>
  %s2 = sext %x to i16
  %r = lshr i16 %s2, zext(C1)

https://bugs.llvm.org/show_bug.cgi?id=46013
2020-06-07 09:33:18 -04:00
Sanjay Patel
b868a972c1 [InstCombine] add tests for bitmask of casted shift; NFC (PR46013) 2020-06-07 09:33:18 -04:00
Simon Pilgrim
320b88c87c AlignmentFromAssumptions.h - reduce includes to forward declarations. NFC. 2020-06-07 13:51:48 +01:00
Simon Pilgrim
fa03afb24a MemorySSAUpdater.h - reduce includes to forward declarations. NFC. 2020-06-07 13:16:31 +01:00
Simon Pilgrim
2b3e248011 DependenceAnalysis.h - reduce AliasAnalysis.h include to forward declaration. NFC.
This requires the replacement of legacy class AliasAnalysis usages with AAResults (which it typedefs to anyhow)
2020-06-07 12:47:37 +01:00
Simon Pilgrim
abbce6f7c9 MustExecute.h - remove unnecessary Instruction.h include. NFC.
We already have the Instruction forward declaration.
2020-06-07 12:10:50 +01:00
Simon Pilgrim
5f8966d8e8 ObjCARCAnalysisUtils.h - remove unused LLVMContext.h include. NFC. 2020-06-07 11:48:46 +01:00
Simon Pilgrim
7ab3b616d7 OrderedInstructions.h - reduce includes to forward declarations. NFC. 2020-06-07 11:44:43 +01:00
Simon Pilgrim
a1faba689a [X86][SSE] Extend ICMP(MOVMSK(BITCAST(X))) tests to allof patterns as well as the existing noneof/anyof patterns. 2020-06-07 11:44:43 +01:00
Simon Pilgrim
b965f99cbd [X86][SSE] Attempt to widen MOVMSK vector input if the signbits are splatted.
As shown on PR37087, if we have a MOVMSK(BICAST(X)) from a wider vector, then by using MOVMSK from the wider type (32/64-bit elements) we can improve the chances of further combines with SimplifyDemandedBits/Elts and on some targets (skylake) can be more efficient.
2020-06-07 11:44:43 +01:00
Florian Hahn
0121122c2a [Matrix] Implement * binary operator for MatrixType.
This patch implements the * binary operator for values of
MatrixType. It adds support for matrix * matrix, scalar * matrix and
matrix * scalar.

For the matrix, matrix case, the number of columns of the first operand
must match the number of rows of the second. For the scalar,matrix variants,
the element type of the matrix must match the scalar type.

Reviewers: rjmccall, anemet, Bigcheese, rsmith, martong

Reviewed By: rjmccall

Differential Revision: https://reviews.llvm.org/D76794
2020-06-07 11:11:27 +01:00
Simon Pilgrim
34905f2907 [X86][SSE] Add MOVMSK tests where we're using a more narrow vector elements than necessary
First step towards fixing PR37087
2020-06-07 10:48:11 +01:00
Xing GUO
897dc4d341 [ObjectYAML][DWARF] Support emitting .debug_ranges section in ELFYAML.
This patch enables yaml2elf to emit the .debug_ranges section.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D81217
2020-06-07 15:47:47 +08:00
Fangrui Song
a7a8160485 [gcov] Improve tests and lower the minimum supported version to gcov 3.4
global-ctor.ll no longer checks what it intended to check
(@_GLOBAL__sub_I_global-ctor.ll needs a !dbg to work).
Rewrite it.

gcov 3.4 and gcov 4.2 use the same format, thus we can lower the version
requirement to 3.4
2020-06-06 23:11:32 -07:00
Fangrui Song
c36c2475a2 [gcov] Delete unneeded code 2020-06-06 20:36:46 -07:00
James Y Knight
ae071ee9e2 Simplify MachineVerifier's block-successor verification.
There's two properties we want to verify:

1. That the successors returned by analyzeBranch are in the CFG
   successor list, and
2. That there are no extraneous successors are in the CFG successor
   list.

The previous implementation mostly accomplished this, but in a very
convoluted manner.

Differential Revision: https://reviews.llvm.org/D79793
2020-06-06 22:30:51 -04:00
James Y Knight
f92fad214d MachineBasicBlock::updateTerminator now requires an explicit layout successor.
Previously, it tried to infer the correct destination block from the
successor list, but this is a rather tricky propspect, given the
existence of successors that occur mid-block, such as invoke, and
potentially in the future, callbr/INLINEASM_BR. (INLINEASM_BR, in
particular would be problematic, because its successor blocks are not
distinct from "normal" successors, as EHPads are.)

Instead, require the caller to pass in the expected fallthrough
successor explicitly. In most callers, the correct block is
immediately clear. But, in MachineBlockPlacement, we do need to record
the original ordering, before starting to reorder blocks.

Unfortunately, the goal of decoupling the behavior of end-of-block
jumps from the successor list has not been fully accomplished in this
patch, as there is currently no other way to determine whether a block
is intended to fall-through, or end as unreachable. Further work is
needed there.

Differential Revision: https://reviews.llvm.org/D79605
2020-06-06 22:30:51 -04:00
Ben Shi
1bcdec3cb9 [RISCV] Fix a typo in RISCVISelLowering.cpp
The 9th parameter of "static bool CC_RISCV(...)" is isFixed, not isRet.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D81333
2020-06-06 18:41:00 -07:00
Mike Edwards
1e5cc34a44 [LIT] NFC adding max-failures option to lit documentation.
Differential Revision: https://reviews.llvm.org/D81337
2020-06-06 18:26:45 -07:00
Craig Topper
a6f53c3183 [X86] Correct some isel patterns for v1i1 KNOT/KANDN/KXNOR.
The KNOT pattern was missing. The others were
looking for a v1i1 -1 instead of a vector all ones.
2020-06-06 17:25:56 -07:00
Fangrui Song
6a5c7ac5ca [gcov] Delete XFAIL: host-byteorder-big-endian for test/Transforms/GCOVProfiling/{exit-block.ll,function-numbering.ll} 2020-06-06 11:59:31 -07:00
LLVM GN Syncbot
34ec4ad872 [gn build] Port 8422bc9efcb 2020-06-06 18:22:19 +00:00
Fangrui Song
b665acc337 [gcov] Support big-endian .gcno and simplify version handling in .gcda 2020-06-06 11:01:47 -07:00
Jonas Paulsson
27037aea90 [SystemZ] Implement -fstack-clash-protection
Probing of allocated stack space is now done when this option is passed. The
purpose is to protect against the stack clash attack (see
https://www.qualys.com/2017/06/19/stack-clash/stack-clash.txt).

Review: Ulrich Weigand

Differential Revision: https://reviews.llvm.org/D78717
2020-06-06 18:38:36 +02:00
Matt Arsenault
6e2d326243 AMDGPU/GlobalISel: Fix test failure in release build
The annoying behavior where the output is different due to the
legality check struck again, plus the subtarget predicate wasn't
really correctly set for DS FP atomics.

Some of the FP min/max instructions seem to be in the gfx6/gfx7
manuals, but IIRC this might have been one of the cases where the
manual got ahead of the actual hardware support, but I've left these
as-is for now since the assembler tests seem to expect them.
2020-06-06 11:01:18 -04:00
Simon Pilgrim
55c9e54358 EHPersonalities.h - reduce Triple.h include to forward declaration. NFC.
Move implicit include dependencies down to source files.
2020-06-06 15:48:31 +01:00
Sanjay Patel
4644aeb774 [DAGCombiner] clean-up FMA+FMUL folds; NFC
D80801 suggests some readability improvements before mocing this block.
2020-06-06 10:32:54 -04:00