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1876 Commits

Author SHA1 Message Date
Jim Grosbach
628ae663ef ARM assembler support for the target-specific .req directive. 
rdar://10549683

llvm-svn: 146543
 2011-12-14 02:16:11 +00:00
Jim Grosbach
089ad574d8 Thumb2 assembler aliases for "mov(shifted register)" 
rdar://10549767

llvm-svn: 146520
 2011-12-13 22:45:11 +00:00
Jim Grosbach
bd33fc6efd ARM LDM/STM system instruction variants. 
rdar://10550269

llvm-svn: 146519
 2011-12-13 21:48:29 +00:00
Jim Grosbach
7db50010cc Test for 146516 
llvm-svn: 146517
 2011-12-13 21:06:59 +00:00
Jim Grosbach
13d3509445 ARM thumb2 parsing of "rsb rd, rn, #0". 
rdar://10549741

llvm-svn: 146515
 2011-12-13 20:50:38 +00:00
Jim Grosbach
dfec87fe2f ARM NEON two-operand aliases for VQDMULH. 
llvm-svn: 146514
 2011-12-13 20:40:37 +00:00
Jim Grosbach
0ba5ba4535 ARM pre-UAL NEG mnemonic for convenience when porting old code. 
llvm-svn: 146511
 2011-12-13 20:23:22 +00:00
Akira Hatanaka
23f439aca1 Add test/MC/Mips/dg.exp. 
llvm-svn: 146472
 2011-12-13 04:12:49 +00:00
Akira Hatanaka
a9290d5ab9 Move direct object emitter test to directory test/MC/Mips. Rename it to 
elf-relsym.ll.

llvm-svn: 146470
 2011-12-13 03:50:34 +00:00
Nick Lewycky
90a4c39a28 Don't rely on a particular version string for llvm. 
llvm-svn: 146456
 2011-12-13 00:34:14 +00:00
Jan Sjödin
b9e2da0d9a XOP instructions and encoding tests. 
llvm-svn: 146407
 2011-12-12 19:37:49 +00:00
Roman Divacky
a450b8b2c8 Add support for gnu_indirect_function. 
llvm-svn: 146377
 2011-12-12 17:34:04 +00:00
Chandler Carruth
afb8199f38 Don't assume things about the exact details of the LLVM version number, 
such as what VCS information is attached.

llvm-svn: 146333
 2011-12-10 21:40:31 +00:00
Rafael Espindola
9b9d35cc05 Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gas 
does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.

llvm-svn: 146311
 2011-12-10 02:28:43 +00:00
Jim Grosbach
356ad6d232 ARM assembly aliases for BIC<-->AND (immediate). 
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.

rdar://10550057

llvm-svn: 146283
 2011-12-09 22:02:17 +00:00
Jim Grosbach
489e81da30 ARM assembly parsing and encoding for VLD2 with writeback. 
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.

Add tests for the instruction variants now supported.

llvm-svn: 146278
 2011-12-09 21:28:25 +00:00
Rafael Espindola
b5c511f7b7 Handle reloc_signed_4byte in here. Not doing so was a regression from my 
previous commit. It is strange that we see it in 32 bits. We already
have a fixme about it.

llvm-svn: 146273
 2011-12-09 19:57:29 +00:00
Kevin Enderby
63cf89d532 The second part of support for generating dwarf for assembly source files. This 
generates the dwarf Compile Unit DIE and a dwarf subprogram DIE for each
non-temporary label.

The next part will be to get the clang driver to enable this when assembling
a .s file.  rdar://9275556

llvm-svn: 146262
 2011-12-09 18:09:40 +00:00
Rafael Espindola
82e22767cf Handle the case of the magical _GLOBAL_OFFSET_TABLE_ showing up in a 
symbol difference. This matches gas behavior and fixes PR11513.

We still don't handle _GLOBAL_OFFSET_TABLE_ in data sections.

llvm-svn: 146238
 2011-12-09 03:03:58 +00:00
Jim Grosbach
62873cae5f ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough. 
llvm-svn: 146194
 2011-12-08 22:19:04 +00:00
Jim Grosbach
a33fa8aa88 ARM VSHR implied destination operand form aliases. 
llvm-svn: 146192
 2011-12-08 22:06:06 +00:00
Jim Grosbach
af9cc198cf Tidy up a bit. 
llvm-svn: 146190
 2011-12-08 22:04:40 +00:00
Jim Grosbach
78020c4642 ARM VSUB implied destination operand form aliases. 
llvm-svn: 146182
 2011-12-08 20:56:26 +00:00
Jim Grosbach
957be45ccf Tidy up a bit. 
llvm-svn: 146181
 2011-12-08 20:53:19 +00:00
Jim Grosbach
a33af36947 ARM VQADD implied destination operand form aliases. 
llvm-svn: 146179
 2011-12-08 20:49:43 +00:00
Jim Grosbach
405e213008 ARM a few more VMUL implied destination operand form aliases. 
llvm-svn: 146177
 2011-12-08 20:42:35 +00:00
Jim Grosbach
e1fe053f6e ARM NEON two-operand aliases for VSHL(immediate). 
llvm-svn: 146125
 2011-12-08 01:30:04 +00:00
Jim Grosbach
3e9384b103 ARM NEON two-operand aliases for VSHL(register). 
llvm-svn: 146123
 2011-12-08 01:12:35 +00:00
Jim Grosbach
3b4d5c0510 ARM optional destination operand variants for VEXT instructions. 
llvm-svn: 146114
 2011-12-08 00:43:47 +00:00
Jim Grosbach
0c64182f7c Tidy up. 
llvm-svn: 146113
 2011-12-08 00:41:54 +00:00
Jim Grosbach
c1cf417595 ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm". 
llvm-svn: 146111
 2011-12-08 00:31:07 +00:00
Jim Grosbach
6146f79b7d ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands. 
For 'gas' compatibility.

llvm-svn: 146106
 2011-12-07 23:40:58 +00:00
Jim Grosbach
dd3788b044 ARM two-operand aliases for VAND/VEOR/VORR instructions. 
llvm-svn: 146095
 2011-12-07 23:08:12 +00:00
Jim Grosbach
da0a3e310a ARM two-operand aliases for VADDW instructions. 
llvm-svn: 146093
 2011-12-07 23:01:10 +00:00
Jim Grosbach
ecf9c2bb21 ARM two-operand aliases for VADD instructions. 
llvm-svn: 146091
 2011-12-07 22:52:54 +00:00
Jim Grosbach
2f57374e32 Darwin assembler improved relocs when w/o subsections_via_symbols. 
When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.

llvm-svn: 146054
 2011-12-07 19:46:59 +00:00
Jim Grosbach
1ccae84fa7 Thumb2 alias for long-form pop and friends. 
rdar://10542474

llvm-svn: 146046
 2011-12-07 18:32:28 +00:00
Jim Grosbach
81cb9952c9 ARM support the .arm and .thumb directives for assembly mode switching. 
llvm-svn: 146042
 2011-12-07 18:04:19 +00:00
Jim Grosbach
3352ab97ca ARM NEON VCLT(register) is a pseudo aliasing VCGT(register). 
llvm-svn: 146039
 2011-12-07 17:51:15 +00:00
Jim Grosbach
61d2b8b2f9 Tidy up. Move MachO tests to MachO directory. 
llvm-svn: 146038
 2011-12-07 17:50:28 +00:00
NAKAMURA Takumi
ed2be25205 test/MC: Introduce MC/MachO/ARM, and relocate relax-thumb2-branches.s into it. 
FIXME: Restore more other arch-dependent MachO tests. (eg. r126401 and r133856)
llvm-svn: 145925
 2011-12-06 06:48:26 +00:00
Jim Grosbach
5b4f7d74de ARM mode 'mul' operand ordering tweak. 
Same as r145922, just for ARM mode.

llvm-svn: 145923
 2011-12-06 05:28:00 +00:00
Jim Grosbach
dc7d42f559 Thumb2: MUL two-operand form encoding operand order fix. 
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.

rdar://10532439

llvm-svn: 145922
 2011-12-06 05:03:45 +00:00
Jim Grosbach
8bdbe92631 Thumb2 encoding choice correction for PLD. 
Using encoding T1 for offset of #0 and encoding T2 for #-0.

rdar://10532413

llvm-svn: 145919
 2011-12-06 04:49:29 +00:00
NAKAMURA Takumi
ea8cc0e506 test/MC: Move relax-thumb2-branches.s from MC/MachO/ to MC/ARM. 
MC/MachO assumes x86.

llvm-svn: 145916
 2011-12-06 03:56:05 +00:00
Jim Grosbach
0fd3f58ea2 Fix ARM handling of tBcc branch relaxation. 
rdar://10069056

llvm-svn: 145885
 2011-12-06 01:08:19 +00:00
Jim Grosbach
74bbb6454e Tweak ADDrr fix. Bad check for explicit .w 
llvm-svn: 145863
 2011-12-05 22:27:04 +00:00
Jim Grosbach
6584358d09 Update tests for r145860. Add a few new ones. 
llvm-svn: 145861
 2011-12-05 22:21:28 +00:00
Jim Grosbach
655b017748 Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions. 
rdar://10529348

llvm-svn: 145851
 2011-12-05 21:06:26 +00:00
Jim Grosbach
9c017fb254 ARM assembly parsing for the rest of the VMUL data type aliases. 
Finish up rdar://10522016.

llvm-svn: 145846
 2011-12-05 20:29:59 +00:00